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| datasheet value-line two-channel ac?97 codecs stac9750/9751 idt? 1 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs overview value-line stereo ac'97 codecs with headphone drive and spdif outputs. features full duplex stereo 18-bit adcs and 20-bit dacs ac?97 rev 2.2 compliant high performance ? technology spdif output crystal elimination circuit headphone amplifier independent sample rates for adcs & dacs (hardware srcs) 20db or 30db microphone boost capability 90db snr line-line 5-wire ac-link protocol compliance digital-ready architecture general purpose i/o +3.3 v (stac9751) and +5 v (stac9750) analog power supply options pin compatible with stac9700/21/56/66 idt surround (ss3d) stereo enhancement energy saving dynamic power modes key specifications analog line_out snr: 90db digital dac snr: 89db digital adc snr: 85db full-scale total harmonic distortion: 0.005% crosstalk between input channels: -70db spurious tone rejection: 100db related materials data sheet reference designs for mb, cnr, acr and pci applications audio precision performance plots description idt's stac9750/9751 are general purpose, full duplex, audio codecs conforming to the analog component spec- ification of ac'97 (audio codec 97 component specifica- tion rev. 2.2). they have 18-bit adcs and 20-bit dacs. the stac9750/9751 incorporate idt's proprietary ? tech- nology to achieve a dac snr in excess of 89db. the dacs, adcs and mixer are integrated with analog i/ os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. the stac9750/9751 include digital input/output capability for support of modern pc systems and also an output that supports the spdif format. the stac9750/9751 is a standard 2-channel stereo codec. with idt?s headphone drive capability, head- phones can be driven with no external amplifier. the stac9750/9751 may be used as a secondary codec, with the stac9700/21/44/56/08/84/66 as the pri- mary, in a multiple codec configuration conforming to the ac'97 rev. 2.2 specification. this configuration can provide the true six-channel, ac-3 playback required for dvd appli- cations. the stac9750/9751 communicates via the five-wire ac-link to any digital component of ac'97, providing flexi- bility in the audio system design. the stac9750/9751 supports general purpose input/out- put (gpio), as well as spdif output. these digital i/o options provide for a number of advanced architectural implementations, with volume controls and digital mixing capabilities built directly into the codec. packaged in an ac'97 compliant 48-pin tqfp, the stac9750/9751 can be placed on the motherboard, daughter boards, pci, amr, cnr, or acr cards.
stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 2 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs table of contents 1. product brief .............................................................................................................. ........ 5 1.1. features ................................................................................................................. ........................... 5 1.2. description .............................................................................................................. .......................... 5 1.3. stac9750/9751 block diagram .............................................................................................. .......... 6 1.4. key specifications ....................................................................................................... ...................... 7 1.5. related materials ........................................................................................................ ...................... 7 1.6. additional support ....................................................................................................... ...................... 7 2. characteristics/specifications .................................................................................. 8 2.1. electrical specifications ................................................................................................ ..................... 8 2.2. ac timing characteristics ................................................................................................ ............... 15 3. typical connection diagram ....................................................................................... 19 4. ac-link .................................................................................................................... ............... 20 4.1. clocking ................................................................................................................. .......................... 20 4.2. reset .................................................................................................................... ........................... 20 5. digital interface .......................................................................................................... .... 21 5.1. ac-link digital serial interface protocol ................................................................................ ......... 21 5.2. ac-link low power mode ................................................................................................... ............ 29 5.3. waking up the ac-link .................................................................................................... ................ 30 6. stac9750/9751 mixer ........................................................................................................ .. 31 6.1. analog mixer input ....................................................................................................... ................... 33 6.2. analog mixer output ...................................................................................................... .................. 33 6.3. spdif digital mux ........................................................................................................ ................... 33 6.4. pc beep implementation ................................................................................................... ............. 33 6.5. programming registers .................................................................................................... ............... 34 7. low power modes ............................................................................................................ 56 8. multiple codec support ...............................................................................................58 8.1. primary/secondary codec selection ........................................................................................ .... 58 8.2. secondary codec register access definitions ............................................................................. 5 9 9. testability ................................................................................................................ .......... 60 10. pin description ........................................................................................................... ..... 61 10.1. digital i/o ............................................................................................................. .......................... 62 10.2. analog i/o .............................................................................................................. ....................... 63 10.3. filter/references/gpio .................................................................................................. ............... 64 10.4. power and ground signals ................................................................................................ ........... 64 11. ordering information .................................................................................................. 65 12. package drawings ......................................................................................................... 6 6 12.1. 48-pin lqfp ............................................................................................................. ..................... 66 13. solder reflow profile ...............................................................................................67 13.1. standard reflow profile data ............................................................................................ ............ 67 13.2. pb free process - package classification reflow temperatures ................................................. 68 14. appendix a: split independent power supply operation .............................. 69 15. appendix b: programming registers .....................................................................71 16. revision history .......................................................................................................... ... 72 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 3 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs list of figures figure 1. stac9750/9751 block diagram ........................................................................................ .............. 6 figure 2. cold reset timing .................................................................................................. ....................... 15 figure 3. warm reset timing .................................................................................................. ..................... 15 figure 4. clocks timing ...................................................................................................... .......................... 16 figure 5. data setup and hold timing ......................................................................................... ................ 17 figure 6. signal rise and fall times timing .................................................................................. .............. 17 figure 7. ac-link low power mode timing ...................................................................................... ........... 18 figure 8. ate test mode timing ............................................................................................... ................... 18 figure 9. stac9751 typical connection diagram ................................................................................ ....... 19 figure 10. ac-link to its companion controller ............................................................................... ............ 20 figure 11. ac'97 standard bi-directional audio frame ......................................................................... ....... 22 figure 12. ac-link audio output frame ........................................................................................ .............. 22 figure 13. start of an audio output frame .................................................................................... ............... 23 figure 14. stac9750/9751 audio input frame ................................................................................... ........ 26 figure 15. start of an audio input frame ..................................................................................... ................ 26 figure 16. stac9750/9751 powerdown timing ................................................................................... ...... 29 figure 17. stac9750 2-channel mixer functional diagram .................................................................. 31 figure 18. stac9751 2-channel mixer functional diagram ....................................................................... 32 figure 19. example of stac9750/9751 powerdown/powerup flow ........................................................... 56 figure 20. stac9750/9751 powerdown/powerup flow with analog still active ........................................ 57 figure 21. stac9750/9751 pin description drawing ............................................................................. ...... 61 figure 22. package drawing - 48-pin lqfp ...................................................................................... ............ 66 figure 23. reflow profile .................................................................................................... .......................... 67 figure 24. stac9750/9751 split independent power supply operation typical connection diagram ....... 70 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 4 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs list of tables table 1. stac9751 analog performance characteristics .......................................................................... ... 13 table 2. cold reset specifications ............................................................................................ .................... 15 table 3. warm reset specifications ............................................................................................ .................. 15 table 4. clocks specifications ................................................................................................ ....................... 16 table 5. clock mode configuration ............................................................................................. .................. 16 table 6. data setup and hold specifications ................................................................................... ............. 17 table 7. signal rise and fall times specifications ............................................................................ ........... 17 table 8. ac-link low power mode timing specifications ......................................................................... ... 18 table 9. ate test mode specifications ......................................................................................... ................ 18 table 10. stac9750/9751 available data streams ................................................................................ ...... 21 table 11. command address port bit assignments ................................................................................ ...... 23 table 12. command data port bit assignments ................................................................................... ........ 24 table 13. status address port bit assignments ................................................................................. ........... 27 table 14. status data port bit assignments .................................................................................... .............. 27 table 15. programming registers ............................................................................................... .................. 34 table 16. play master volume register ......................................................................................... ............... 35 table 17. pc_beep register .................................................................................................... .................... 36 table 18. analog mixer input gain register .................................................................................... .............. 37 table 19. record select control registers ..................................................................................... .............. 39 table 20. record gain registers .............................................................................................. ................... 39 table 21. general purpose register ............................................................................................ ................. 40 table 22. 3d control registers ............................................................................................... ..................... 40 table 23. powerdown status registers .......................................................................................... ............... 42 table 24. extended audio id ................................................................................................... ...................... 43 table 25. slot assignment relationship between spsa1 and spsa0 ........................................................... 45 table 26. stac9750/9751 amap compliant ........................................................................................ ......... 45 table 27. hardware supported sample rates ..................................................................................... ......... 45 table 28. spdif control ....................................................................................................... ........................ 46 table 29. extended moden status and control ................................................................................... .......... 47 table 31. gpio pin polarity/type register ..................................................................................... .............. 48 table 32. gpio pin sticky register ............................................................................................ ................... 48 table 30. gpio pin configuration register ..................................................................................... .............. 48 table 33. gpio pin mask register .............................................................................................. .................. 49 table 35. digital audio control register ...................................................................................... .................. 50 table 34. gpio pin status register ............................................................................................ .................. 50 table 36. adc data on ac link ................................................................................................. .................. 52 table 37. mic boost select .................................................................................................... ........................ 52 table 38. analog current adjust ............................................................................................... .................... 53 table 39. gpio access registers (74h) ......................................................................................... ............... 54 table 40. low power modes ..................................................................................................... .................... 56 table 41. codec id selection .................................................................................................. ................... 58 table 42. secondary codec register access slot 0 bit definitions ........................................................... 59 table 43. digital connection signals .......................................................................................... ................... 62 table 44. analog connection signals ........................................................................................... ................ 63 table 45. filtering and voltage references .................................................................................... .............. 64 table 46. power and ground signals ............................................................................................ ................ 64 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 5 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 1. product brief 1.1. features full duplex stereo 18-bit adc and 20-bit dac ac?97 rev 2.2-compliant high performance ? technology spdif output crystal elimination circuit headphone amplifier independent sample rates for adcs & dacs (hardware srcs) 20db or 30db microphone boost capability 90db snr line-line 5-wire ac-link protocol compliance digital-ready architecture general purpose i/o +3.3 v (stac9751) and +5 v (stac9750) analog power supply options pin compatible with the stac9700/21/44/08/56/66/52 idt surround (ss3d) stereo enhancement energy saving dynamic power modes 1.2. description idt's stac9750/9751 are general purpose 18-bit adc, 20-bit dac, full duplex, audio codecs con- forming to the analog component specification of ac'97 (audio codec ?97 component specification rev. 2.2). the stac9750/9751 incorporate idt's proprietary ? technology to achieve a dac snr in excess of 90 db. the dacs, adcs, and mixer are integrated with analog i/os, which include four analog line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output channel. the stac9750/9751 include digital input/output capability for support of modern pc systems with an output that supports the spdif format. the stac9750/9751 is a standard 2-chan- nel stereo codec. with idt?s headphone drive capability, headphones can be driven with no exter- nal amplifier. the stac9750/9751 may be used as a secondary codec, with the stac9700/21/44/ 56/08/84/66 as the primary, in a multiple codec configuration conforming to the ac'97 rev. 2.2 specification. this configuration can provide the true six-channel, ac-3 playback required for dvd applications. the stac9750/9751 communicates via the five-wire ac-link to any digital component of ac'97, providing flexibility in the audio system design. packaged in an ac'97 compliant 48-pin lqfp, the stac9750/9751 can be placed on a motherboard, daughter boards, pci, amr, cnr, or acr cards. the stac9750/9751 block diagram is illustrated in figure 1. it provides variable sample rate digi- tal-to-analog (da) and analog-to-digital (ad) conversion, mixing, and analog processing. supported audio sample rates include 48 khz, 44.1 khz, 32 khz, 22.05 khz, 16 khz, 11.025 khz, and 8 khz; additional rates are supported in the stac9750/9751 soft audio drivers. the digital interface com- municates with the ac'97 controller via the five-wire ac-link and contains the 64-word by 16-bit reg- stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 6 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs isters. the two dacs convert the digital stereo pcm-out content to audio. the mixer block combines the pcm_out with any analog sources, to drive the line_out and hp_out outputs. the mono_out delivers either microphone only, or a mono mix of sources from the mixer. the stereo variable sample rate adcs provide record capability for any mix of mono or stereo sources, and deliver a digital stereo pcm_in signal back to the ac-link. the microphone input and mono input can be recorded simultaneously, thus allowing for an all digital output in support of the digital ready initiative. all adcs operate at 18-bit resolution and dacs at 20-bit resolution. for a digital ready record path, the microphone is connected to the left channel adc while the mono output of the stereo mixer is connected to right channel adc. make sure the microphone input is not connected to the stereo mixer when in this mode. the stac9750/9751 supports general purpose input/output (gpio), as well as spdif output. these digital i/o options provide for a number of advanced architectural implementations, with vol- ume controls and digital mixing capabilities built directly into the codec. the stac9750/9751 is designed primarily to support stereo (2-speaker) audio. true ac-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-codec option avail- able in the stac9750/9751 to support multiple codecs in an ac'97 architecture. additionally, the stac9750/9751 provides for a stereo enhancement feature, idt surround 3d (ss3d). ss3d pro- vides the listener with several options for improved speaker separation beyond the normal 2/ 4-speaker arrangements. together with the logic component (controller or advanced core logic chip-set) of ac'97, stac9750/ 9751 can be soundblaster ? and windows sound system ? compatible with idt?s wdm driver for win 98/2k/me/xp. soundblaster is a registered trademark of creative labs. windows is a registered trademark of microsoft corporation. 1.3. stac9750/9751 block diagram figure 1. stac9750/9751 block diagram hp_out ac-link digital interface registers 64x16 bits sync bit_clk sdata_out sdata_in reset# power management dac dac adc adc pcm out dacs pcm in adcs 4 stereo sources 2 mono sources mono_out mic boost 0,20 or 30 db mic1 stereo mono mixer analog mixing and gain control m u x mic2 line_out multi-codec cid0 cid1 spdif variable sample rate 20-bit dacs and 18-bit adcs stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 7 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 1.4. key specifications analog line_out snr: 90 db digital dac snr: 89 db digital adc snr: 85 db full-scale total harmonic distortion: 0.005% crosstalk between input channels: -70 db spurious tone rejection: 100 db 1.5. related materials product brief reference designs for mb, amr, cnr, and acr applications audio precision performance plots 1.6. additional support additional product and company information can be obtained by going to the idt website at: www.idt.com stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 8 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 2. characteristics/specifications 2.1. electrical specifications 2.1.1. absolute maximum ratings: stresses above the ratings listed below can cause permanent damage to the stac9750/9751. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. 2.1.2. recommended operation conditions item pin maximum rating maximum supply voltage vdd 5.5 volts output current per pin 4 ma, except vref_out = 5ma voltage on any pin relative to ground vss - 0.3 v to vdd + 0.3 v operating temperature 0 o c to +70 o c storage temperature -55 o c to +125 o c soldering temperature 260 o c for 10 seconds * soldering temperature information for all available packages begins on page 67. parameter min. typ. max. units power supply voltage digital - 3.3 v 3.135 3.3 3.465 v analog - 5 v 4.75 5 5.25 v analog - 3.3 v 3.135 3.3 3.465 v ambient operating temperature 0 +70 c case temperature t case (48-lqfp) +90 c esd: the stac9750/9751 is an esd (electrostatic discharge) sensitive device. the human body and test equipment can accumulate and discharge electrostatic charges up to 4000 volts without detection. even though the stac9750/9751 implements internal esd protection circuitry, proper esd precautions should be followed to avoid damaging the functionality or performance. stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 9 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 2.1.3. power consumption parameter min typ max unit digital supply current + 3.3 v digital - 30 - ma analog supply current (at reset state) + 5 v analog - 35 - ma + 3.3 v analog - 35 - ma power down status (individually asserted) all pr measurements taken while unmuted. all paths unmuted +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 50 44 33 -ma pr0 +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 42 39 22 -ma pr1 +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 41 38 28 -ma pr2 +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 32 29 12 -ma pr3 +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 23 19 12 -ma pr4 +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 50 44 0.2 -ma pr5 +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 50 44 12 -ma pr6 +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 38 36 33 -ma pr0 & pr1 +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 35 35 12 -ma pr0, pr1, pr2, pr6 +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 5 5 12 -ma pr0, pr1, pr2, pr3, pr6 +5 v analog supply current +3.3 v analog supply current +3.3 v digital supply current - 0.6 0.6 12 -ma stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 10 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 2.1.4. revision comparison 2.1.5. ac-link static digital specifications (t ambient = 25 oc, dvdd = 3.3 v 5%, avss=dvss=0 v; 50 pf external load) ca3 cc1 % of savings analog digital analog digital analog digital 5 v 3.3 v 3.3 v 5 v 3.3 v 3.3 v 5 v 3.3 v 3.3 v no pr 78 69 27 50 44 33 36% 36% -22% pr0 62 56 23 42 39 22 32% 30% 4% pr1 63 52 24 41 38 28 35% 27% -17% pr2 48 42 27 32 29 12 33% 31% 56% pr3 40 35 21 23 19 12 43% 46% 43% pr4 76 68 1 50 44 0.2 34% 35% 80% pr5 75 68 7.5 50 44 12 33% 35% -60% pr6 97 61 27 38 36 33 61% 41% -22% pr bit individually asserted. all pr measurements taken while unmuted. parameter symbol min typ max unit input voltage range vin -0.30 - dvdd + 0.30 v low level input range vil - - 0.35xdvdd v high level input voltage vih 0.65xdvdd - - v high level output voltage voh 0.90xdvdd - - v low level output voltage vol - - 0.1xdvdd v input leakage current (ac-link inputs) - -10 - 10 a output leakage current (ac-link outputs - hi-z) - -10 - 10 a output buffer drive current - - 4 - ma stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 11 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 2.1.6. stac9750 analog performance characteristics (t ambient = 25 oc, avdd = 5.0 v 5%, dvdd = 3.3 v 5%, avss=dvss=0 v; 1 khz input sine wave; sample frequency = 48 khz; 0db = 1 vrms, 10 k ?/ 50 pf load, testbench characterization bw: 20 hz ? 20 khz, 0db settings on all gain stages) parameter min typ max unit full scale input voltage: all analog inputs except microphone - 1.0 - vrms microphone inputs (note 1) - 0.03 - vrms full scale output: line output - 1.0 - vrms pcm (dac) to line_out - 1.0 vrms mono_out - 1.0 - vrms headphone_out (32 ? load) (peak) -50-mw analog s/n: (note 2) cd to line_out - 90 - db other to line_out - 90 - db d/a to line_out - 89 - db line_in to a/d with high pass filter enabled - 85 - db analog frequency response (note 3) 20 - 20,000 hz total harmonic distortion: (note 4) cd to line_out - 89 - db other to line_out - 89 - db d/a to line_out (full scale) - 89 - db line_in to a/d with high pass filter enabled 84 - - db headphone_out 74 80 - db a/d & d/a digital filter pass band (note 5) 20 - 19,200 hz a/d & d/a digital filter transition band 19,200 - 28,800 hz a/d & d/a digital filter stop band 28,800 - - hz a/d & d/a digital filter stop band rejection (note 6) 100 - - db dac out-of-band rejection (note 7) 55 - - db group delay (48khz sample rate) - 1 ms any analog input to line_out crosstalk (10 khz signal frequency) - 70 - db any analog input to line_out crosstalk (1 khz signal frequency) - 100 - db spurious tone rejection - 100 - db attenuation, gain step size - 1.5 - db input impedance (note 8) - 50 - k ? input capacitance - 15 - pf vref_out - 0.5 x avdd - v stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 12 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs note: 1. with +30 db boost on, 1.0 vrms with boost off. 2. ratio of full scale signal to idle channel noise output is measured ?a weighted? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 3. 1db limits for line output & 0 db gain. 4. ratio of full scale signal to thd+n output with -3db signal, measured ?a weighted? over a 20 khz bw, 48 khz sample frequency. 5. 0.25db limits 6. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 7. the integrated out-of-band noise generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. 8. for all inputs except pc beep. interchannel gain mismatch adc - - 0.5 db interchannel gain mismatch dac - - 0.5 db parameter min typ max unit stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 13 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 2.1.7. stac9751 analog performance characteristics (t ambient = 25 oc, avdd = dvdd = 3.3 v 5%, avss=dvss=0 v; 1 khz input sine wave; sample fre- quency = 48 khz; 0db = 1 vrms, 10 k ?/ 50 pf load, testbench characterization bw: 20 hz ? 20 khz, 0db settings on all gain stages) parameter min typ max unit full scale input voltage: all analog inputs except microphone - 1.0 - vrms microphone inputs (note 1) - 0.03 - vrms full scale output: line output - 0.5 - vrms pcm (dac) to line_out 0.5 vrms mono_out - 0.5 - vrms headphone_out (32 ? load) (peak) - 12.5 - mw analog s/n: (note 2) cd to line_out - 90 - db other to line_out - 90 - db d/a to line_out - 89 - db line_in to a/d with high pass filter enabled - 85 - db analog frequency response (note 3) 20 - 20,000 hz total harmonic distortion: (note 4) cd to line_out - 89 - db other to line_out - 89 - db d/a to line_out (full scale) - 89 - db line_in to a/d with high pass filter enabled - 84 - db headphone_out 74 80 - db a/d & d/a digital filter pass band (note 5) 20 - 19,200 hz a/d & d/a digital filter transition band 19,200 - 28,800 hz a/d & d/a digital filter stop band 28,800 - - hz a/d & d/a digital filter stop band rejection (note 6) 100 - - db dac out-of-band rejection (note 7) 55 - - db group delay (48 khz sample rate) - - 1 ms any analog input to line_out crosstalk (10 khz signal frequency) - 70 - db any analog input to line_out crosstalk (1 khz signal frequency) - 100 - db spurious tone rejection - 100 - db attenuation, gain step size - 1.5 - db input impedance (note 8) - 50 - k ? input capacitance - 15 - pf vref_out -0.5 x avdd- v table 1. stac9751 analog performance characteristics stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 14 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs note: 1. with +30 db boost on, 1.0 vrms with boost off. 2. ratio of full scale signal to idle channel noise output is measured ?a weighted? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio).0 db gain, 20 khz bw, 48 khz sample frequency 1 db limits. 3. 1db limits for line output & 0 db gain. 4. ratio of full scale signal to thd+n output with -3db signal, measured ?a weighted? over a 20 khz bw, 48 khz sample frequency. 5. 0.25db limits 6. stop band rejection determines filter requirements. out-of-band rejection determines audible noise. 7. the integrated out-of-band noise generated by the dac process, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. 8. for all inputs except pc beep. interchannel gain mismatch adc - - 0.5 db interchannel gain mismatch dac - - 0.5 db gain drift - 100 - ppm/oc parameter min typ max unit table 1. stac9751 analog performance characteristics (continued) stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 15 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 2.2. ac timing characteristics (t ambient = 25 c, avdd = 3.3 v or 5 v 5%, dvdd = 3.3 v 5%, avss = dvss = 0 v; 50 pf external load) 2.2.1. cold reset figure 2. cold reset timing note: bit_clk and sdatain are in a high impedance state during reset. 2.2.2. warm reset figure 3. warm reset timing table 2. cold reset specifications parameter symbol min typ max units reset# active low pulse width tres_low 1.0 - - s reset# inactive to bit_clk startup delay trst2clk 162.8 - - ns table 3. warm reset specifications parameter symbol min typ max units sync active high pulse width tsync_high 1.0 1.3 - s sync inactive to bit_clk startup delay tsync2clk 162.8 - - ns tres_low trst2clk reset# bit_clk sdata_in tsync_high tsync_2clk sync bit_clk stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 16 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 2.2.3. clocks figure 4. clocks timing the stac9750/9751 supports several clock frequency inputs as described in the following table. in general, when a 24.576 mhz clock xtal is not used, the xtal_out pin should be tied to ground. this short to ground configures the part into an alternate clock mode and enables an on board pll. table 4. clocks specifications parameter symbol min typ max units bit_clk frequency - 12.288 - mhz bit_clk period tclk_period - 81.4 - ns bit_clk output jitter - 750 - ps blt_clk high pulse width (note 1) tclk_high 36 40.7 45 ns bit_clk low pulse width (note 1) tclk_low 36 40.7 45 ns sync frequency - 48.0 - khz sync period tsync_period - 20.8 - s sync high pulse width tsync_high - 1.3 - s sync low pulse width tsync_low - 19.5 - s note: 1. worst case duty cycle restricted to 45/55. table 5. clock mode configuration xtl_out pin config cid1 pin config cid0 pin config clock source input codec mode codec id xtal float float 24.576 mhz xtal p 0 xtal or open float pulldown 12.288 mhz bit_clk s 1 xtal or open pulldown float 12.288 mhz bit_clk s 2 xtal or open pulldown pulldown 12.288 mhz bit_clk s 3 short to ground float float 14.31818 mhz source p 0 short to ground float pulldown 27 mhz source p 0 short to ground pulldown float 48 mhz source p 0 short to ground pulldown pulldown 24.576 mhz source p 0 sync bit_clk tclk_high tclk_low tclk_period tsync_high tclk_period tsync_low stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 17 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 2.2.4. data setup and hold (47.5-75 pf external load) figure 5. data setup and hold timing 2.2.5. signal rise and fall times (75pf external load; from 10% to 90% of vdd) figure 6. signal rise and fall times timing table 6. data setup and hold specifications parameter symbol min typ max units setup to falling edge of bit_clk tsetup 10 - - ns hold from falling edge of bit_clk thold 10 - - ns note: setup and hold time parameters for sdata_in are with respect to the ac'97 controller. table 7. signal rise and fall times specifications parameter symbol min typ max units bit_clk rise time triseclk - - 6 ns bit_clk fall time tfallclk - - 6 ns sdata_in rise time trisedin - - 6 ns sdata_in fall time tfalldin - - 6 ns bit_clk t hold t setup sdata_out sdata_in sync tco v ih v il v oh v ol bit_clk sdata_in t fa llc lk t ris e c lk t ris e d in t fa lld in stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 18 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 2.2.6. ac-link low power mode timing figure 7. ac-link low power mode timing 2.2.7. ate test mode figure 8. ate test mode timing note: 1. all ac-link signals are normally low through the trailing edge of reset#. bringing sdata_out high for the trailing edge of reset# causes the stac9750/9751 ac-link outputs to go high-impedance, which is suitable for ate in-circuit testing. 2. once the test mode has been entered, the stac9750/9751 must be issued another reset# with all ac-link signals low to return to the normal operating mode. 3. # denotes active low. table 8. ac-link low power mode timing specifications parameter symbol min typ max units end of slot 2 to bit_clk, sdata_in low ts2_pdown - - 1.0 s table 9. ate test mode specifications parameter symbol min typ max units setup to trailing edge of reset# (also applies to sync) tsetup2rst 15.0 - - ns rising edge of reset# to hi-z delay toff - - 25.0 ns bit_clk sdata_in n o te : b it _ c l k n o t to s c a le ts2_pdown don't care d a ta p r 4 write to 0x20 slot 2 slot 1 sdata_out sync tsetup2rst hi-z toff reset# sdata_out sdata_in, bit_clk stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 19 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 3. typical connection diagram figure 9. stac9751 typical connection diagram note: 1. see appendix a for specific connection requirements prior to operation. 2. see figure 24 on page 70 for split supply connections. 3. pin 48: to enable spdif, use an 1 kw-10 kw external pulldown. to disable spdif, use an 1 kw-10 kw external pullup. do not leave pin 48 floating. 4. the cd_gnd signal is an ac signal return for the two cd input channels. it is normally biased at about 2.5v. the name of the pin in the ac97 specification is cd_gnd, and this has confused many designers. it should not have any dc path to gnd. connecting the cd_gnd signal directly to ground will change the internal bias of the entire codec, and cause significant distortion. if there is no analog cd input, then this pin can be no-connect. 0.1 f 1 f 0.1 f 0.1 f 10 f 0.1 f 2 ? * ferrite bead* *suggested 3.3v 5% avdd1 avdd2 dvdd1 dvdd2 xtl_in xtl_out 9 2 3 27 pf 27 pf 24.576 mhz 1 38 25 pc_beep 12 phone 13 aux_l 14 aux_r 15 video_l 16 video_r 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 41 cap2 32 *optional 0.1 f 1 f* 820 pf 29 30 afilt1 afilt2 820 pf avss1 avss2 26 42 4 7 dvss1 dvss2 hp_out_r *terminate ground plane as close to codec as possible analog ground digital ground hp_out_l 39 37 mono_out 36 line_out_r 35 line_out_l 43 gpio0 44 gpio1 40 hp_comm 48 spdif 34 nc 33 nc 31 nc 0.1 f 1 f* *optiona l 27 vref vrefout eapd cid1 cid0 28 47 46 45 11 reset# 10 sync 24 sdata_in bit_clk sdata_out 5 6 8 27 pf 22 ? emi filter *optional stac9751 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 20 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 4. ac-link figure 10 shows the ac-link point to point serial interconnect between the stac9750/9751 and its companion controller. all digital audio streams and command/status information are communicated over this ac-link. see ?digital interface? on page 21 for details. figure 10. ac-link to its companion controller 4.1. clocking stac9750/9751 derives its clock internally from an externally connected 24.576 mhz crystal or an oscillator, through the xtal_in pin. synchronization with the ac'97 controller is achieved through the bit_clk pin at 12.288 mhz. the beginning of all audio sample packets, or ?audio frames?, transferred over ac-link is synchro- nized to the rising edge of the ?sync? signal driven by the ac'97 controller. data is transitioned on ac-link on every rising edge of bit_clk, and subsequently sampled by the receiving side on each immediately following falling edge of bit_clk. 4.2. reset there are 3 types of resets: 1. a ?cold? reset where all stac9750/9751 logic and registers are initialized to their default state 2. a ?warm? reset where the contents of the stac9750/9751 register set are left unaltered 3. a ?register? reset which only initializes the stac9750/9751 registers to their default states after signaling a reset to the stac9750/9751 , the ac'97 controller should not attempt to play or cap- ture audio data until it has sampled a ?codec ready? indication via register 26h from the stac9750/9751 . for proper reset operation sdata_out should be 0 during cold reset. sync digital dc'97 controller ac'97 codec bit_clk sdata_out sdata_in reset# xtal_in xtal_out a stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 21 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 5. digital interface 5.1. ac-link digital seri al interface protocol the stac9750/9751 communicates to the ac'97 controller via a 5-wire, digital, serial, ac-link inter- face, which is a bi-directional, fixed rate, serial pcm digital stream. all digital audio streams, com- mands and status information are communicated over this point-to-point serial interconnect. the ac-link handles multiple input and output audio streams, as well as control register accesses using a time division multiplexed (tdm) scheme. the ac'97 controller synchronizes all ac-link data trans- action. table 10 shows the data streams available on the stac9750/9751 : synchronization of all ac-link data transactions is handled by the ac'97 controller. the stac9750/ 9751 drives the serial bit clock onto ac-link. the ac'97 controller then qualifies with a synchroniza- tion signal to construct audio frames. sync, fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk). bit_clk, fixed at 12.288 mhz, provides the necessary clocking granularity to support twelve 20-bit outgoing and incoming time slots. ac-link serial data is transitioned on each rising edge of bit_clk. the receiver of ac-link data, stac9750/9751 for outgoing data and ac'97 controller for incoming data, samples each serial bit on the falling edges of bit_clk. the ac-link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit posi- tions) time slot (slot 0) wherein each bit conveys a ?slot-valid? tag for its corresponding time slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. if a slot is tagged invalid, it is the responsibility of the source of the data, (stac9750/9751 for the input stream, ac'97 controller for the output stream), to stuff all bit positions with 0s during that slot?s active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is defined as the ?tag phase?. the remainder of the audio frame where sync is low is defined as the ?data phase?. additionally, for power savings, all clock, sync, and data signals can be halted by the controller. table 10. stac9750/9751 available data streams pcm playback 2 output slots 2 channel composite pcm output stream pcm record data 2 input slots 2 channel composite pcm input stream control 2 output slots control register write port status 2 input slots control register read port stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 22 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs figure 11. ac'97 standard bi-directional audio frame 5.1.1. ac-link audio output frame (sdata_out) the audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the stac9750/9751 dac inputs, and control registers. each audio output frame supports up to twelve 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16 bits that are used for ac-link protocol infrastructure. within slot 0, the first bit is a global bit (sdata_out slot 0, bit 15) which flags the validity for the entire audio frame. if the ?valid frame? bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. the next 12 bit positions sampled by the stac9750/9751 indi- cate which of the corresponding 12 times slots contain valid data. in this way data streams of differ- ing sample rates can be transmitted across ac-link at its fixed 48 khz audio frame rate. the following diagram illustrates the time slot based ac-link protocol. figure 12. ac-link audio output frame a new audio output frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the stac9750/9751 samples the assertion of sync. this following edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising edge of bit_clk, the ac'97 controller transitions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by the stac9750/ 9751 on the following falling edge of bit_clk. this sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams, are time aligned. outgoing streams incoming streams sync tag phase data phase pcm left cmd adr na pcm lsurr pcm lfe pcm ralt tag cmd data pcm rt pcm ctr pcm rsurr pcm lalt rsvd pcm left status adr na rsvd rsvd rsvd tag status data pcm rt na rsvd rsvd rsvd sync bit_clk sdata_out slot1 slot2 end of previous audio frame slot(12) "0" 19 data phase 20.8 us (48 khz) tag phase 12.288 mhz time slot "valid" bits slot 1 slot 2 slot 3 slot 12 ("1" = time slot contains valid pcm data) cid1 cid0 valid "0" 19 19 "0" frame 19 "0" "0" stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 23 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs figure 13. start of an audio output frame sdata_out?s composite stream is msb justified (msb first) with all non-valid slots? bit positions stuffed with 0s by the ac'97 controller. when mono audio sample streams are sent from the ac'97 controller, it is necessary that both left and right sample stream time slots be filled with the same data. 5.1.1.1. slot 1: command address port the command port is used to control features and monitor status (see audio input frame slots 1 and 2) of the stac9750/9751 functions including, but not limited to, mixer settings and power man- agement (refer to the control register section of this specification). the control interface architecture supports up to sixty-four 16-bit read/write registers, addressable on even byte boundaries. only the even registers (00h, 02h, etc.) are valid. odd accesses are con- sidered invalid and return 0000h. audio output frame slot 1 communicates control register address and write/read command informa- tion to the stac9750/9751. the first bit (msb) sampled by stac9750/9751 indicates whether the current control transaction is a read or a write operation. the following 7 bit positions communicate the targeted control register address. the trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the ac'97 controller. table 11. command address port bit assignments bit description comments 19 read/write command 1= read, 0=write 18:12 control register index sixty-four 16-bit locations, addressed on even byte boundaries 11:0 reserved stuffed with 0s sync bit_clk sdata_out slot1 slot2 e nd of previous audio fram e v a lid fram e sync asserted first sdata_out bit of fram e stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 24 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 5.1.1.2. slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the cur- rent command port operation is a write cycle (as indicated by slot 1, bit 19). if the current command port operation is a read cycle, then the entire slot time must be stuffed with 0s by the ac'97 controller. 5.1.1.3. slot 3: pcm playback left channel audio output frame slot 3 is the composite digital audio left playback stream. in a typical ?games compatible? pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac'97 controller or host processor) with music synthesis output samples. if a sample stream of reso- lution less than 20-bits is transferred, the ac'97 controller must stuff all trailing non-valid bit positions within this time slot with 0s. 5.1.1.4. slot 4: pcm playback right channel audio output frame slot 4 is the composite digital audio right playback stream. in a typical ?games compatible? pc this slot is composed of standard pcm (.wav) output samples digitally mixed (on the ac'97 controller or host processor) with music synthesis output samples. if a sample stream of reso- lution less than 20-bits is transferred, the ac'97 controller must stuff all trailing non-valid bit positions within this time slot with 0s. 5.1.1.5. slot 5: reserved audio output frame slot 5 is reserved for modem operation and is not used by the stac9750/9751. 5.1.1.6. slot 6: pcm center channel audio output frame slot 6 is the composite digital audio center stream used in a multi-channel appli- cation where the stac9750/9751 is programmed to accept the primary dac pcm data from slots 6 and 9. please refer to the register programming section for details on the multi-channel programming options. 5.1.1.7. slot 7: pcm left surround channel audio output frame slot 7 is the composite digital audio left surround stream. in the default state, the stac9750/9751 accepts pcm data from slots 7 and 8 for the surround dacs, for output to the dac_out pins. as a programming option, pcm data from slots 7 and 8 may be used to supply data to the primary dacs when slots 6 and 9 are used to drive the surround dacs. please refer to the register programming section for details on the multi-channel programming options. table 12. command data port bit assignments bit description comments 19:4 control register write data stuffed with 0s if current operation is a read 3:0 reserved stuffed with 0s stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 25 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 5.1.1.8. slot 8: pcm right surround channel audio output frame slot 8 is the composite digital audio right surround stream. as a programming option, pcm data from slots 7 and 8 may be used to supply data to the primary dacs. please refer to the register programming section for details on the multi-channel programming options. 5.1.1.9. slot 9: pcm low frequency channel audio output frame slot 9 is the composite digital audio low frequency stream used in a multi-channel application where the stac9750/9751 is programmed to accept the primary dac pcm data from slots 6 and 9. please refer to the register programming section for details on the multi-channel pro- gramming options. 5.1.1.10. slot 10: pcm alternate left audio output frame slot 10 is the composite digital audio alternate left stream used in a multi-channel applications. please refer to the register programming section for details on the multi channel pro- gramming options. 5.1.1.11. slot 11: pcm alternate right audio output frame slot 11 is the composite digital audio alternate right stream used in a multi-chan- nel applications. please refer to the register programming section for details on the multi channel programming options. 5.1.1.12. slot 12: reserved audio output frame slot 12 is reserved for modem operations and is not used by the stac9750/ 9751. 5.1.2. ac-link audio input frame (sdata_in) the audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac'97 controller. as is the case for audio output frame, each ac-link audio input frame consists of twelve 20-bit time slots. slot 0 is a special reserved time slot containing 16 bits that are used for ac-link protocol infrastructure. within slot 0, the first bit is a global bit (sdata_in slot 0, bit 15) which flags whether the stac9750/ 9751 is in the ?codec ready? state or not. if the ?codec ready? bit is a 0, this indicates that stac9750/9751 is not ready for normal operation. this condition is normal following the de-asser- tion of power on reset, for example, while stac9750/9751?s voltage references settle. when the ac-link ?codec ready? indicator bit is a 1, it indicates that the ac-link and stac9750/9751 con- trol/status registers are in a fully operational state. the ac'97 controller must further probe the pow- erdown control status register (refer to mixer register section) to determine exactly which subsections, if any, are ready. stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 26 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs prior to any attempts at putting stac9750/9751 into operation the ac'97 controller should poll the first bit in the audio input frame (sdata_in slot 0, bit 15) for an indication that stac9750/9751 has become ?codec ready?. once the stac9750/9751 is sampled ?codec ready?, the next 12 bit positions sampled by the ac'97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. the following diagram illustrates the time slot based ac-link protocol. figure 14. stac9750/9751 audio input frame a new audio input frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. immediately following the falling edge of bit_clk, the stac9750/9751 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the stac9750/9751 transi- tions sdata_in into the first bit position of slot 0 (?codec ready? bit). each new bit position is pre- sented to ac-link on a rising edge of bit_clk and subsequently sampled by the ac'97 controller on the following falling edge of bit_clk. this sequence ensures that data transitions, and subse- quent sample points for both incoming and outgoing data streams are time aligned. figure 15. start of an audio input frame sdata_in's composite stream is msb justified (msb first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by stac9750/9751. sdata_in data is sam- pled on the falling edges of bit_clk. 5.1.2.1. slot 1: status address port the status port is used to monitor status for stac9750/9751 functions including, but not limited to, mixer settings and power management. sync bit_clk sdata_in slot1 slot2 end of previous audio frame slot(12) "0" 19 data phase 20.8 us (48 khz) tag phase 12.288 mhz time slot "valid" bits slot 1 slot 2 slot 3 slot 12 ("1" = time slot contains valid pcm data) valid "0" 19 19 "0" frame 19 "0" "0" "0" "0" sync bit_clk sdata_in slot1 slot2 end of previous audio fram e codec ready sync asserted first sdata_out bit of fram e stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 27 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs audio input frame slot 1?s stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (assuming that slots 1 and 2 had been tagged ?valid? by stac9750/ 9751 during slot 0.) the first bit (msb) generated by stac9750/9751 is always stuffed with a 0. the following 7 bit posi- tions communicate the associated control register address, and the trailing 12 bit positions are stuffed with 0 by the stac9750/9751. 5.1.2.2. slot 2: status data port the status data port delivers 16-bit control register read data. if slot 2 is tagged ?invalid? by stac9750/9751 , then the entire slot will be stuffed with 0's. 5.1.2.3. slot 3: pcm record left channel audio input frame slot 3 is the left channel output of stac9750/9751 input mux, post-adc. stac9750/9751 adcs are implemented to support 18-bit resolution. stac9750/9751 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. 5.1.2.4. slot 4: pcm record right channel audio input frame slot 4 is the right channel output of stac9750/9751 input mux, post-adc. stac9750/9751 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. 5.1.2.5. slot 5: reserved audio input frame slot 5 is reserved for modem operation and is not used by the stac9750/9751. this slot is always stuffed with 0. table 13. status address port bit assignments bit description comments 19 reserved stuffed with 0 18:12 control register index echo of register index for which data is being returned 11:2 slot request see sections below 1:0 reserved stuffed with 0 table 14. status data port bit assignments bit description comments 19:4 control register read data stuffed with 0 if tagged ?invalid? 3:0 reserved stuffed with 0 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 28 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 5.1.2.6. slot 6: pcm left record channel audio input frame slot 6 is the left channel output of stac9750/9751 input mux, post-adc. stac9750/9751 adcs are implemented to support 18-bit resolution. stac9750/9751 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. see section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.7. slot 7: pcm left record channel audio input frame slot 7 is the left channel output of stac9750/9751 input mux, post-adc. stac9750/9751 adcs are implemented to support 18-bit resolution. stac9750/9751 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. see section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.8. slot 8: pcm right record channel audio input frame slot 8 is the right channel output of stac9750/9751 input mux, post-adc. stac9750/9751 adcs are implemented to support 18-bit resolution. stac9750/9751 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0's to fill out its 20-bit time slot. see section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.9. slot 9: pcm right record channel audio input frame slot 9 is the right channel output of stac9750/9751 input mux, post-adc. stac9750/9751 adcs are implemented to support 18-bit resolution. stac9750/9751 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. see section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.10. slot 10: pcm left record channel audio input frame slot 10 is the left channel output of stac9750/9751 input mux, post-adc. stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 29 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs stac9750/9751 adcs are implemented to support 18-bit resolution. stac9750/9751 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. see section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.11. slot 11: pcm right record channel audio input frame slot 11 is the right channel output of stac9750/9751 input mux, post-adc. stac9750/9751 adcs are implemented to support 18-bit resolution. stac9750/9751 outputs its adc data (msb first), and stuffs any trailing non-valid bit positions with 0 to fill out its 20-bit time slot. see section 6.5.25; page 51 for slot configurations and register settings. 5.1.2.12. slot 12: reserved audio input frame slot 12 is reserved for modem operation and is not used by the stac9750/9751. this slot is always stuffed with 0. 5.2. ac-link low power mode the stac9750/9751 ac-link can be placed in the low power mode by programming register 26h to the appropriate value. both bit_clk and sdata_in will be brought to, and held at a logic low volt- age level. the ac'97 controller can wake up the stac9750/9751 by providing the appropriate reset signals. figure 16. stac9750/9751 powerdown timing bit_clk and sdata_in are transitioned low immediately (within the maximum specified time) fol- lowing the decode of the write to the powerdown register (26h) with pr4. when the ac'97 control- ler driver is at the point where it is ready to program the ac-link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame (all sources of audio input have been neutralized). sync bit_clk sdata_out note: bit_clk not to scale sdata_in tag write to 0x20 slot 2 per frame data pr4 tag slot 2 per frame stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 30 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs the ac'97 controller should also drive sync, and sdata_out low after programming the stac9750/9751 to this low power mode. 5.3. waking up the ac-link once the stac9750/9751 has halted bit_clk, there are only two ways to ?wake up? the ac-link. both methods must be activated by the ac'97 controller. the ac-link protocol provides for a ?cold ac'97 reset?, and a ?warm ac'97 reset?. the current power down state would ultimately dictate which form of reset is appropriate. unless a ?cold? or ?register? reset (a write to the reset register) is performed, wherein the ac'97 registers are initialized to their default values, registers are required to keep state during all power down modes. once powered down, re-activation of the ac-link via re-assertion of the sync signal must not occur for a minimum of 4 audio frame times following the frame in which the power down was triggered. when ac-link powers up it indicates readiness via the codec ready bit (input slot 0, bit 15). cold reset - a cold reset is achieved by asserting reset# for the minimum specified time, and then bringing reset# back high. the reset occurs on the rising edge when reset# is deas- serted. by asserting and deasserting reset#, bit_clk and sdata_in will be activated, or re-acti- vated as the case may be, and all stac9750/9751 control registers will be initialized to their default power-on-reset values. note: reset# is an asynchronous input. (# denotes active low) warm reset - a warm reset will re-activate the ac-link without altering the current stac9750/9751 register values. a warm reset is signaled by driving sync high for a minimum of 1 s in the absence of bit_clk. note: within normal audio frames, sync is a synchronous input. however, in the absence of bit_clk, sync is treated as an asynchronous input used in the generation of a warm reset to the stac9750/ 9751. stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 31 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6. stac9750/9751 mixer the stac9750/9751 includes analog and digital mixers for maximum flexibility. the analog mixer is designed to the ac'97 specification to manage the playback and record of all digital and analog audio sources in the pc environment. the analog mixer also includes several extensions of the ac?97 specification to support ?all analog record? capability as well as ?pop bypass? mode for all digital playback. the analog sources include: system audio : digital pcm input and output for business, games and multimedia cd/dvd : analog cd/dvd-rom audio with internal connections to codec mixer mono microphone : choice of desktop microphone, with programmable boost and gain speakerphone : use of system microphone and speakers for telephone, dsvd, and video con- ferencing video : tv tuner or video capture card with internal connections to codec mixer aux/synth : analog fm or wavetable synthesizer, or other internal source the digital mixer includes inputs for the pcm dac and the recorded adc output figure 17. stac9750 2-channel mixer functional diagram 0ah 0ch 0eh 10h 12h 16h 14h pc_beep phone cd aux video linein mic1 mic2 20h:d8 20 or 30 db allanalog vs allrecord 6eh:d12 -6db mux adc 04h mono volume master volume 3d line_out 3d hp_out 02h 06h mux 1ch 20h:d15 analog audio sources slot select slot select mux pcm to spdif spdif pcmout 2ah:d5-d4 28h: d5-d4 pcmin ganged3dcontrol 20h:d13 22h:d2-d3 1ah -6db monoanalog stereoanalog digital key 20h:d9 adcrecord 6e:d2 mux vol mute vol mute vol mute vol mute vol mute vol mute vol mute vol mute mux dac 3d record volume 6ah:d1 18h headphone volume mono_out 0eh:d6 slot select stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 32 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs figure 18. stac9751 2-channel mixer functional diagram source function connection pc_beep pc beep pass through to line_out from pc_beep output phone mono input from telephony subsystem mic1 desktop microphone from microphone jack mic2 second microphone from second microphone jack line_in external audio source from line-in jack cd audio from cd-rom cable from cd-rom video audio from tv tuner or video camera cable from tv or vidcap card aux upgrade synth or other external source internal connector pcm out digital audio output from ac'97 controller ac-link destination function connection hp_out stereo mix of all sources to headphone out jack line_out stereo mix of all sources to output jack mono_out microphone or mono analog mixer output to telephony subsystem pcm in digital data from the codec to the ac'97 controller ac-link spdif spdif digital audio output to spdif output connector 0ah 0ch 0eh 10h 12h 16h 14h pc_beep phone cd aux video linein mic1 mic2 20h:d8 allanalog vs allrecord 6eh:d12 -6db mux 04h mono volume master volume 02h 06h mux 1ch 20h:d15 analog audio sources 1ah -6db monoanalog stereoanalog digital key 20h:d9 adcrecord 0eh:d6 mux vol mute vol mute vol mute vol mute vol mute vol mute vol mute vol mute mux 3d record volume +6db -6db -6db -6db -6db -6db -6db 18h headphone volume -6db 20 or 30 db 6e:d2 slot select slot select mux pcmout 2ah:d5-d4 dac adc 3d line_out 3d hp_out pcmin ganged3dcontrol 20h:d13 22h:d2-d3 mono_out slot select 28h: d5-d4 pcm to spdif spdif 6ah:d1 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 33 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.1. analog mixer input the mixer provides recording and playback of any audio sources or output mix of all sources. the stac9750/9751 supports the following input sources: any mono or stereo source mono or stereo mix of all sources two-channel input with mono output reference (microphone + stereo mix) note: all unused inputs should be tied together connected to ground through a capacitor (0.1 f suggested). 6.2. analog mixer output the mixer generates three distinct outputs: a stereo mix of all sources for output to the line_out and hp_out a stereo mix of all analog sources for recording microphone only or mono mix of all sources for mono_out note: mono output of stereo mix is attenuated by -6 db. 6.3. spdif digital mux the stac9750/9751 incorporates a digital output that supports spdif formats. a multiplexer deter- mines which of two digital input streams are used for the digital output conversion process. these two streams include the pcm out data from the audio controller and the adc recorded output. the normal analog line_out signal can be converted to the spdif formats by using the internal adc to record the ?mix? output, which is the combination of all analog and all digital sources. in the case of digital controllers with support for 4 or more channels, the spdif output mode can be used to sup- port compressed 6-channel output streams for delivery to home theater systems. these can be routed on alternate ac-link slots to the spdif output, while the standard 2-channel output is deliv- ered as selected by bits d5 and d4 in register 6e. if the digital controller supports 6 channels, a spdif output with 4 analog channels can also be configured (in a multi-codec setup). for more information for spdif please see 6.5.12.2; page 44. pin 48: to enable spdif, use an 1 k ? -10 k ? external pulldown. to disable spdif, use an 1k ? -10 k ? external pullup. do not leave pin 48 floating. 6.4. pc beep implementation pc beep is active on power up and defaults to an un-muted state. the pc_beep input is routed directly to the mono_out, line_out and hp_out pins of the codec. because the pc_beep input drive is often a full scale digital signal, some resistive attenuation of the pc_beep input is rec- ommended to keep the beep tone within reasonable volume levels. the user should mute this input before using any other mixer input because the pc beep input can contribute noise to the lineout during normal operation. this style of pc beep is related to the ac?97 specification rev 2.2. to use the analog pc beep, a value of 00h to bits f[7:0](d[12:5]) disables the digital pc beep generation. pv[3:0] (d[4:1]) controls the volume level from 0 to 45db of attenuation in 3db steps. stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 34 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5. programming registers * register 74h is used for gpio control in revision ca3. table 15. programming registers address name default location 00h reset 6990h 6.5.1; page 35 02h master volume 8000h 6.5.2.1; page 35 04h hp_out mixer volume 8000h 6.5.2.2; page 35 and 35 06h master volume mono 8000h 6.5.2.3; page 36 0ah pc beep mixer volume 0000h 6.5.3; page 36 0ch phone mixer volume 8008h 6.5.4.1; page 37 0eh microphone mixer volume 8008h 6.5.4.2; page 37 10h line in mixer volume 8808h 6.5.4.3; page 37 12h cd mixer volume 8808h 6.5.4.4; page 38 14h video mixer volume 8808h 6.5.4.5; page 38 16h aux mixer volume 8808h 6.5.4.6; page 38 18h pcm out mixer volume 8808h 6.5.4.7; page 38 1ah record select 0000h 6.5.5; page 38 1ch record gain 8000h 6.5.6; page 39 20h general purpose 0000h 6.5.7; page 39 22h 3d control 0000h 6.5.8; page 40 24h audio interrupt 0000h 6.5.9; page 41 26h powerdown control/status 000fh 6.5.10; page 41 28h extended audio id 0205h 6.5.11; page 42 2ah extended audio control/status 0400h 6.5.12; page 44 2ch pcm dac rate bb80h 6.5.14; page 46 32h pcm lr adc rate bb80h 6.5.15; page 46 3ah spdif control 2a00h 6.5.16; page 46 3eh extended modem control/status 0100h 6.5.17; page 47 4ch gpio pin configuration 0003h 6.5.18; page 47 4eh gpio pin polarity/type ffffh 6.5.19; page 48 50h gpio pin sticky 0000h 6.5.20; page 48 52h gpio wake-up 0000h 6.5.21; page 49 54h gpio pin status 0000h 6.5.22; page 49 6ah digital audio control 0000h 6.5.16; page 46 6ch revision code 00xxh 6.5.24; page 51 6eh analog special 0000h 6.5.25; page 51 70h 72h enable 0000h 6.5.25.6; page 53 72h analog current adjust 0000h 6.5.25.7; page 53 74h* gpio current access 0000h 6.5.26; page 54 76h 78h enable 0000h 6.5.27.1; page 54 78h clock access 0000h 6.5.27.2; page 55 7ch vendor id1 8384h 6.5.28.1; page 55 7eh vendor id2 76xxh 6.5.28.2; page 55 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 35 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.1. reset (00h) default: 6990h writing any value to this register performs a register reset, which causes all registers to revert to their default values. reading this register returns the id code of the part. 6.5.2. play master volume registers (index 02h, 04h, and 06h) these registers manage the output signal volumes. register 02h controls the stereo line_out master volume (both right and left channels), register 04h controls the headphone out master vol- ume, and register 06h controls the mono volume output. each step corresponds to 1.5 db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. ml5 through ml0 is for left channel level, mr5 through mr0 is for the right channel and mm5 through mm0 is for the mono out channel. when bits d5 and d13 are set in any of these registers it automatically writes all 1 to the next lower 5-bits. the default value is 8000h for registers 02h, 04h, and 06h, which corresponds to 0 db attenuation with mute on. 6.5.2.1. master volume (02h) default: 8000h note: if optional bits d13 & d5 of register 02h are set to 1, then the corresponding attenuation is set to 46.5db and the register reads will produce 1fh as a value for this attenuation/gain block. 6.5.2.2. headphone out volume (04h) default: 8000h d15 d14 d13 d12 d11 d10 d9 d8 rsrvd4 se4 se3 se2 se1 se0 id9 id8 d7 d6 d5 d4 d3 d2 d1 d0 id7 id6 id5 id4 id3 id2 id1 id0 table 16. play master volume register mute mx5?mx0 function range 0 00 0000 0db attenuation req. 0 01 1111 46.5 attenuation req. 1 xx xxxx db attenuation req. d15 d14 d13 d12 d11 d10 d9 d8 mute rsrvd ml5 ml4 ml3 ml2 ml1 ml0 d7 d6 d5 d4 d3 d2 d1 d0 reserved mr5 mr4 mr3 mr2 mr1 mr0 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 36 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs note: if optional bits d13 & d5 of register 04h are set to 1, then the corresponding attenuation is set to 46.5db and the register reads will produce 1fh as a value for this attenuation/gain block. 6.5.2.3. master volume mono (06h) default: 8000h note: if optional bit d5 of register 06h is set to 1, then the corresponding attenuation is set to 46.5db and the register reads will produce 1fh as a value for this attenuation/gain block. 6.5.3. pc beep mixer volume (index 0ah) default: 0000h note: pc_beep defaults to 0000h, mute off. this register controls the level for the pc beep input. each step corresponds to approximately 3db of attenuation. the msb of the register is the mute bit. when this bit is set to 1, the level for that channel is set at - db. pc_beep supports motherboard implementations. the intention of routing pc_beep through the stac9750/9751 mixer is to eliminate the requirement for an onboard speaker by guaranteeing a connection to speakers connected via the output jack. in order for this to be viable, the pc_beep signal needs to reach the output jack at all times. note: the pc_beep is routed to the mono outputs when the stac9750/9751 is in a reset state. this is so that power on self test (post) codes can be heard by the user in case of a hardware problem with the pc. for further pc_beep implementation details please refer to the ac'97 technical faq sheet. the default value is 0000h, which corresponds to 0 db attenuation with mute off. d15 d14 d13 d12 d11 d10 d9 d8 mute rsrvd hpl5 hpl4 hpl3 hpl2 hpl1 hpl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved hpr5 hpr4 hpr3 hpr2 hpr1 hpr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved mm5 mm4 mm3 mm2 mm1 mm0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved pv3 pv2 pv1 pv0 rsrvd table 17. pc_beep register mute pv3?pv0 function 0 0000 0 db attenuation 0 1111 45 db attenuation 1xxxx db attenuation stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 37 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.4. analog mixer input gain registers (index 0ch - 18h) these registers control the gain/attenuation for each of the analog inputs. each step corresponds to approximately 1.5 db. the msb of the register is the mute bit. when this bit is set to 1 the level for that channel is set at - db. the default value for stereo registers is 8808h, corresponding to 0 db gain with mute on. 6.5.4.1. phone mixer volume (0ch) default: 8008h 6.5.4.2. mic mixer volume (0eh) default: 8008h register 0eh (mic volume register) bit d6 is the mic boost enable. to select between 20db or 30db mic boost, see register 6eh, d2 in section 6.5.25; page 51. 6.5.4.3. line in mixer volume (10h) default: 8808h table 18. analog mixer input gain register mute gx4?gx0 function 0 0 0000 +12 db gain 0 0 1000 0 db gain 0 1 1111 -34.5 db gain d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gn4 gn3 gn2 gn1 gn0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved d7 d6 d5 d4 d3 d2 d1 d0 rsrvd boost_en rsrvd gn4 gn3 gn2 gn1 gn0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 38 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.4.4. cd mixer volume (12h) default: 8808h 6.5.4.5. video mixer volume (14h) default: 8808h 6.5.4.6. aux mixer volume (16h) default: 8808h 6.5.4.7. pcm out mixer volume (18h) default: 8808h 6.5.5. record select (1ah) default: 0000h (corresponding to mic in) d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl4 gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr4 gr3 gr2 gr1 gr0 d15 d14 d13 d12 d11 d10 d9 d8 reserved sl2 sl1 sl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved sr2 sr1 sr0 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 39 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs used to select the record source independently for right and left. 6.5.6. record gain (1ch) default: 8000h (corresponding to 0 db gain with mute on) the 1ch register adjusts the stereo input record gain. each step corresponds to 1.5db. 22.5db cor- responds to 0f0fh. the msb of the register is the mute bit. when this bit is set to 1, the level for that channel(s) is set at - db. 6.5.7. general purpose (20h) default: 0000h table 19. record select control registers bit(s) reset name description 15:11 0 reserved bits not used, should read back 0 10:8 0 sl2:sl0 left channel input select 000 = mic 001 = cd in (left) 010 = video in (left) 011 = aux in (left) 100 = line in (left) 101 = stereo mix (left) 110 = mono mix 111 = phone 7:3 0 reserved bits not used, should read back 0 2:0 0 sr2:sr0 right channel input select 000 = mic 001 = cd in (right) 010 = video in (right) 011 = aux in (right) 100 = line in (right) 101 = stereo mix (right) 110 = mono mix 111 = phone d15 d14 d13 d12 d11 d10 d9 d8 mute reserved gl3 gl2 gl1 gl0 d7 d6 d5 d4 d3 d2 d1 d0 reserved gr3 gr2 gr1 gr0 table 20. record gain registers mute gx3? gx0 function 0 1111 +22.5 db gain 0 0000 0 db gain 1xxxx- gain d15 d14 d13 d12 d11 d10 d9 d8 pop byp rsrvd 3d reserved mix ms d7 d6 d5 d4 d3 d2 d1 d0 lpbk reserved stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 40 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs this register is used to control some miscellaneous functions. below is a summary of each bit and its function. the ms bit controls the mic selector. the lpbk bit enables loopback of the adc output to the dac input without involving the ac-link, allowing for full system performance measurements. 6.5.8. 3d control (22h) default: 0000h this register is used to control the 3d stereo enhancement function, idt surround 3d (ss3d), built into the ac'97 component. note that register bits dp3-dp2 are used to control the separation ratios in the 3d control for line_out. ss3d provides for a wider soundstage extending beyond the nor- mal 2-speaker arrangement. note that the 3d bit in the general purpose register (20h) must be set to 1 to enable ss3d functionality and for the bits in 22h to take effect. the three separation ratios are implemented as shown in table 22. the separation ratio defines a series of equations that determine the amount of depth difference (high, medium, and low) per- ceived during two-channel playback. the ratios provide for options to narrow or widen the sound- stage. table 21. general purpose register bit function 3d 3d stereo enhancement on/off - 1 = on mix mono output select - 0 = mix, 1= mic ms mic select - 0 = mic1, 1 = mic2 pop byp dac bypasses mixer and connects directly to line out lpbk adc/dac loopback mode d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved dp3 dp2 reserved table 22. 3d control registers dp3, dp2 line_out separation ratio 0 0 0 (off) 0 1 3 (low) 1 0 4.5 (med) 1 1 6 (high) stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 41 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.9. audio interrupt (24h) default: 0000h 6.5.10. powerdown ctrl/stat (26h) default: 000fh d15 d14 d13 d12 d11 d10 d9 d8 i4 i3 reserved i0 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved bit(s) reset value r/w name description 15 0 rw i4 0 = interrupt is clear 1 = interrupt is set interrupt event is cleared by writing a 1 to this bit. the interrupt bit will change regardless of condition of interrupt enable (i0) status. an interrupt in the gpi in slot 12 in the ac-link will follow this bit change when interrupt enable (i0) is unmasked. 14 0 ro i3 interrupt cause 0 = no interrupt caused 1 = change in gpio input status these bits will reflect the general cause of the first interrupt event generated. it should be read after interrupt status has been confirmed as interrupting. the information should be used to scan possible interrupting events in proper pages. 13-12 0 rw reserved bits not used, should read back 0 11 0 rw i0 interrupt enable 0 = interrupt generation is masked. 1 = interrupt generation is un-masked. the driver should not un-mask the interrupt unless ensured by the ac ?97 controller that no conflict is possible with modem slot 12 - gpi functionality. some ac?97 2.2 compliant controllers do not support audio codec interrupt infrastructure. in either case, s/w should poll the interrupt status after initiating a sense cycle and wait for sense cycle max delay to determine if an interrupting event has occurred. 10:0 0 ro reserved bits not used, should read back 0 d15 d14 d13 d12 d11 d10 d9 d8 eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 d7 d6 d5 d4 d3 d2 d1 d0 reserved ref anl dac adc stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 42 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs this read/write register is used to program power down states and monitor subsystem readiness. the eapd external control is also supported through this register. 6.5.10.1. ready status the lower half of this register is read only status, a 1 indicating that the subsection is ready. ready is defined as the subsection's ability to perform in its nominal state. when this register is written, the bit values that come in on ac-link will have no effect on read only bits 0-7. when the ac-link ?codec ready? indicator bit (sdata_in slot 0, bit 15) is a 1, it indicates that the ac-link and ac'97 control and status registers are in a fully operational state. the ac'97 controller must further probe this powerdown control/status register to determine exactly which subsections, if any are ready. when this register is written, the bit values that come in on ac-link will have no effect on read only bits 0-7. 6.5.10.2. powerdown controls the stac9750/9751 is capable of operating at reduced power when no activity is required. the state of power down is controlled by the powerdown register (26h). see the section ?low power modes? for more information. 6.5.10.3. external amplifier power down control the eapd bit 15 of the powerdown control/status register (index 26h) directly controls the output of the eapd output (pin 45), and produces a logical 1 when this bit is set to logic high. this function is used to control an external audio amplifier power down. eapd = 0 places approximately 0v on the output pin, enabling an external audio amplifier. eapd = 1 places approximately dvdd on the output pin, disabling the external audio amplifier. audio amplifiers that operate with reverse polarity will likely require an external inverter to maintain software driver compatibility. 6.5.11. extended audio id (28h) default: 0605h table 23. powerdown status registers bit function eapd external amplifier power down ref vref?s up to nominal level anl analog mixers, etc. ready dac dac section ready to playback data adc adc section ready to playback data d15 d14 d13 d12 d11 d10 d9 d8 id1 id0 reserved rev1 rev0 amap ldac d7 d6 d5 d4 d3 d2 d1 d0 sdac cdac dsa1 dsa0 vrm spdif dra vra stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 43 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs the extended audio id register is a read-only register, except for bits d5:d4. id1 and id0 echo the configuration of the codec as defined by the programming of pins 45 and 46 externally. a returned 00 defines the codec as the primary codec, while any other code identifies the codec as one of three secondary codec possibilities. sdac = 0 tells the controller that the stac9750/9751 is a two-channel codec as defined by the intel specification. the amap bit, d9, will return a 1 indicat- ing that the codec supports the optional ?ac?97 2.2 compliant ac-link slot to audio dac map- pings?. the default condition assumes that 00 are loaded in the dsa0 and dsa1 bits of the extended audio id (index 28h). with 00 in the dsax bits, the codec slot assignments are as per the ac?97 specification recommendations. if the dsax bits do not contain 00, the slot assignments are as per the table in the section describing the extended audio id (index 28h). the vra bit, d0, will return a 1 indicating that the codec supports the optional variable sample rate conversion as defined by the ac?97 specification. 1. external cid pin status (from analog) these bits are the logical inversion of the pin polarity (pin 45-46). these bits are zero if xtal_out is grounded with an alternate external clock source in primary mode only. secondary mode can either be through bit clk driven or 24 mhz clock driver with xtal_out floating/shorted. 2. if pin 48 is held high at powerup, this bit will be held to zero, to indicate the spdif is not avail- able. pin 48: to enable spdif, use an 1 k ? -10 k ? external pulldown. to disable spdif, use an 1k ? -10 k ? external pullup. do not leave pin 48 floating. table 24. extended audio id bit name access reset value function 15:14 id [1,0] read only variable 00 = xtal_out grounded (note 1) cid1#, cid0# = xtal_out crystal or floating 13:12 reserved read only 00 reserved 11:10 rev[1:0] read only 01 indicates codec is ac?97 rev 2.2 compliant 9 amap read only 1 multi-channel slot support (always = 1) 8 ldac read only 0 low frequency effect, not supported (always=0) 7 sdac read only 0 surround dac, not supported (always = 0) 6 cdac read only 0 center channel, not supported (always = 0) 5:4 dsa [1,0] read/write 00 dac slot assignment if cid[1:0] = 00 then dsa[1:0] resets to 00 if cid[1:0] = 01 then dsa[1:0] resets to 01 if cid[1:0] = 10 then dsa[1:0] resets to 01 if cid[1:0] = 11 then dsa[1:0] resets to 10 00 = left slot 3, right slot 4 01 = left slot 7, right slot 8 10 = left slot 6, right slot 9 11 = left slot 10, right slot 11 3 vrm read only 0 variable sample rate mic, not supported (always = 0) 2 spdif read only 1 0 = spdif pulled high on reset, spdif disabled 1 = default, spdif enabled (note 2) 1 dra read only 0 double rate audio, not supported (always = 0) 0 vra read only 1 variable sample rates supported (always = 1) stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 44 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.12. extended audio control/status (2ah) default: 0400h 6.5.12.1. variable rate sampling enable the extended audio status control register also contains one active bit to enable or disable the vari- able sampling rate capabilities of the dacs and adcs. if the vra, bit d0, is 1, the variable sample rate control registers (2ch and 32h) are active, and ?on-demand? slot data required transfers are allowed. if the vra bit is 0, the dacs and adcs will operate at the default 48 khz data rate. the stac9750/9751 supports ?on-demand? slot request flags. these flags are passed from the codec to the ac?97 controller in every audio input frame. each time a slot request flag is set (active low) in a given audio frame, the controller will pass the next pcm sample for the corresponding slot in the audio frame that immediately follows. the vra enable bit must be set to 1 to enable ?on-demand? data transfers. if the vra enable bit is not set, the codec will default to 48 khz trans- fers and every audio frame will include an active slot request flag and data is transferred every frame. for variable sample rate output, the codec examines its sample rate control registers, the state of the fifos, and the incoming sdata_out tag bits at the beginning of each audio output frame to determine which slotreq bits to set active (low). slotreq bits are asserted during the current audio input frame for active output slots, which will require data in the next audio output frame. for variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. thus, even in variable sample rate mode, the codec is always the master: for sdata_in (codec to controller), the codec sets the tag bit; for sdata_out (controller to codec), the codec sets the slotreq bit and then checks for the tag bit in the next frame. whenever vra is set to 0, the pcm rate registers (2ch and 32h) are overwritten with bb80h (48 khz). 6.5.12.2. spdif the spdif bit in the extended audio status control register is used to enable and disable the spdif functionality within the stac9750/9751. if the spdif is set to a 1, then the function is enabled and when set to a 0 it is disabled. 6.5.12.3. spcv (spdif configuration valid) the spcv bit is read only and indicates whether or not the spdif system is set up correctly. when spcv is a 0, it indicates the system configuration is invalid and valid if it is a 1. d15 d14 d13 d12 d11 d10 d9 d8 reserved spcv reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved spsa1 spsa0 rsrvd spdif rsrvd vra enable stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 45 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.12.4. spsa1, spsa0 (spdif slot assignment) spsa1 and spsa0 combine to provide the slot assignments for the spdif data. the following details the slot assignment relationship between spsa1 and spsa0. the stac9750/9751 are amap compliant with the following table. 6.5.13. pcm dac rate registers (2ch and 32h) the internal sample rate for the dacs and adcs are controlled by the value in these read/write reg- isters that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in hertz (hz). in vra mode (register 2ah bit d0 = 1), if the value written to these registers is supported, that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample rate is supported and returned. per pc 99 / pc 2001 specification, independent sample rates are supported for record and playback. whenever vra is set to 0, the pcm rate registers (2ch and 32h) will read back with bb80h (48 khz). table 25. slot assignment relationship between spsa1 and spsa0 spsa[1,0] slot assignment comments 00 3 & 4 spdif source data slot assignment 01 7 & 8 2-channel codec primary default 10 6 & 9 4-channel codec primary default 11 10 & 11 6-channel codec primary default table 26. stac9750/9751 amap compliant codec id function spsa = 00 spsa = 01 spsa = 10 spsa = 11 00 2-channel primary w/spdif 3 & 4 7 & 8* 6 & 9 10 & 11 01 2-channel dock codec w/spdif 3 & 4 7 & 8 6 & 9* 10 & 11 10 +2-channel surr w/ spdif 3 & 4 7 & 8 6 & 9* 10 & 11 11 +2-channel cntr/lfe w/ spdif 3 & 4 7 & 8 6 & 9 10 & 11* note: * is the default slot assignment table 27. hardware supported sample rates sample rate sr15-sr0 value 8 khz 1f40h 11.025 khz 2b11h 16 khz 3e80h 22.05 khz 5622h 32 khz 7d00h 44.1 khz ac44h 48 khz bb80h stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 46 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.14. pcm dac rate (2ch) default: bb80h 6.5.15. pcm lr adc rate (32h) default: bb80h 6.5.16. spdif control (3ah) default: 2a00h register 3ah is a read/write register that controls spdif functionality and manages bit fields propa- gated as channel status (or sub-frame in the v case). with exception of v, this register should only be written to when the spdif transmitter is disabled (spdif bit register 2 ah is 0). this ensures that control and status information start up correctly at the beginning of spdif transmission. the default is 2a00h which sets the spdif output sample rate at 48 khz and the normal spdif expectations . d15 d14 d13 d12 d11 d10 d9 d8 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 d7 d6 d5 d4 d3 d2 d1 d0 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 d15 d14 d13 d12 d11 d10 d9 d8 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 d7 d6 d5 d4 d3 d2 d1 d0 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 d15 d14 d13 d12 d11 d10 d9 d8 #v drs spsr1 spsr2 l cc6 cc5 cc4 d7 d6 d5 d4 d3 d2 d1 d0 cc3 cc2 cc1 cc0 pre copy #pcm/audio pro table 28. spdif control bit(s) reset access name description (note 1-2) 15 0 read & write #v validity bit is set indicating each sub-frame?s samples are invalid. if #v is 0, then it indicates that each sub-frame was transmitted and received correctly by the interface. 14 0 read only drs 1 = double rate spdif support (always = 0) 13:12 10 read & write spsr[1,0] spdif sample rate. 00 44.1 khz rate 01 reserved 10 48 khz rate (default) 11 32 khz rate 11 0 read & write l generation level is defined by the iec standard, or as appropriate. (always = 1) stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 47 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 1. if pin 48 is held high at powerup, 28h d2 will be low indicating no spdif available and the regis- ter 3ah will then read back 0000h. pin 48: to enable spdif, use an 1 k ? -10 k ? external pull- down. to disable spdif, use an 1 k ? -10 k ? external pullup. do not leave pin 48 floating. 2. bits d15, d13-d00 of this register cannot be written to without first setting reg 2ah bit d2 = 0 (spdif disabled) and register 28h bit d2 = 1 (spdif available). 6.5.17. extended modem status and control register (3eh) default: 0100h 6.5.18. gpio pin configuration register (4ch) default: 0003h 10:4 0 read & write cc[6, 0] category code is defined by the iec standard or as appropriate by media. 3 0 read & write pre 0 = 0 sec pre-emphasis 1 = pre-emphasis is 50/15 sec 2 0 read & write copy 0 = copyright not asserted 1 = copyright is asserted 1 0 read & write /audio 0 = pcm data 1 = non-audio or non-pcm format 0 0 read & write pro 0 = consumer use of the channel 1 = professional use of the channel d15 d14 d13 d12 d11 d10 d9 d8 reserved pra d7 d6 d5 d4 d3 d2 d1 d0 reserved gpio table 29. extended modem status and control bit(s) access reset value name description 15:9 read only 0 reserved bit not used, should read back 0 8 read / write 1 pra 0 = gpio powered up / enabled 1 = gpio powered down / disabled 7:1 read only 0 reserved bit not used, should read back 0 0 read only 0 gpio 0 = gpio not ready (powered down) 1 = gpio ready (powered up) d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gc1 (gpio1) gc0 (gpio0) table 28. spdif control (continued) bit(s) reset access name description (note 1-2) stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 48 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.19. gpio pin polarity/type register (4eh) default: ffffh 6.5.20. gpio pin sticky register (50h) default: 0000h table 30. gpio pin configuration register bit(s) access reset value name description 15:2 read only 0 reserved bit not used, should read back 0 1 read / write 1 gc1 0 = gpio1 configured as output 1 = gpio1 configured as input 0 read / write 1 gc0 0 = gpio0 configured as output 1 = gpio0 configured as input d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gp1 (gpio1) gp0 (gpio0) table 31. gpio pin polarity/type register bit(s) access reset value name description 15:2 read only 0 reserved bit not used, should read back 0 1 read / write 1 gp1 0 = gpio1 input polarity inverted, cmos output drive. 1 = gpio1 input polarity non-inverted, open-drain output drive. 0 read / write 1 gp0 0 = gpio0 input polarity inverted, cmos output drive. 1 = gpio0 input polarity non-inverted, open-drain output drive. d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gs1 (gpio1) gs0 (gpio0) table 32. gpio pin sticky register bit(s) access reset value name description 15:2 read only 0 reserved bit not used, should read back 0 1 read / write 0 gs1 0 = gpio1 non sticky configuration. 1 = gpio1 sticky configuration. 0 read / write 0 gs0 0 = gpio0 non sticky configuration. 1 = gpio0 sticky configuration. stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 49 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.21. gpio pin mask register (52h) default: 0000h 6.5.22. gpio pin status register (54h) default: 0000h d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gw1 (gpio1) gw0 (gpio0) table 33. gpio pin mask register bit(s) access reset value name description 15:2 read only 0 reserved bit not used, should read back 0 1 read / write 0 gw1 0 = gpio1 interrupt not passed to gpio_int slot 12. 1 = gpio1 interrupt is passed to gpio_int slot 12. 0 read / write 0 gw0 0 = gpio0 interrupt not passed to gpio_int slot 12. 1 = gpio0 interrupt is passed to gpio_int slot 12. d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved gi1 (gpio1) gi0 (gpio0) stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 50 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.23. digital audio control (6ah) default: 0000h this read/write register is used to program the digital mixer input status. in the default state, the pcm dac path is enabled and the adc record inputs are disabled. the do1 and do0 bits control the input source for the pcm to digital output converters. the table describes the available options. table 34. gpio pin status register bit(s) access reset value name description 15:2 read only 0 reserved bit not used, should read back 0 1 read / write x gi1 when gpio1 is configured as output and register 74h bit[0] = 0 (default), the value of this register will be placed on the gpio1 pad. when gpio1 is configured as output and register 74h bit[0] =1, the gpio1 pad will get its value from slot12. when gpio1 is configured as input and configured as a sticky writing a 1 does nothing, writing a 0 clears this bit. when gpio1 is configured as input this register reflects the value on the gpio1 pad after interpretation of the polarity and sticky configurations. 0 read / write x gi0 when gpio0 is configured as output and register 74h bit[0] = 0 (default), the value of this register will be placed on the gpio0 pad. when gpio0 is configured as output and register 74h bit[0] =1, the gpio0 pad will get its value from slot12. when gpio0 is configured as input and configured as a sticky writing a 1 does nothing, writing a 0 clears this bit. when gpio0 is configured as input this register reflects the value on the gpio0 pad after interpretation of the polarity and sticky configurations. d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved do1 do0 table 35. digital audio control register bit(s) reset name description 15:2 0 reserved bits not used, should read back 0 10 do1 spdif digital output source selection: do1 = 0; pcm data from the ac-link to spdif do1 = 1; adc record data to spdif 0 0 do0 always reads zero stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 51 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.24. revision code (6ch) default: 00xxh the device revision code register (index 6ch) contains a software readable revision-specific code used to identify performance, architectural, or software differences between various device revi- sions. bits 7:0 of the revision code register are user readable; bits 15:8 are not used at this time and will return zeros when read. this value can be used by the audio driver, or miniport driver in the case of win98 ? wdm approaches, to adjust software functionality to match the feature-set of the stac9750/9751. this will allow the software driver to identify any required operational differences between the existing stac9750/9751 and future versions. 6.5.25. analog special (6eh) default: 0000h the analog special register has several bits used to control various functions specific to the stac9750/9751. 6.5.25.1. all mix the ac?97 all_mix, bit d12 of register 6eh, controls the record source when the stereo mix option is selected for recording. if the ac?97 mode is default logic 1, the ?stereo mix record? option will include the sum of the analog sources with or without 3d enhancement, and the main pcm dac output. if the ?all analog record? option is selected, the stereo mix record option will include the sum of the analog sources only, with or without 3d enhancement. the ?ac?97 mode? is useful for recording all sound sources. the ?all analog record? mode is useful in conjunction with the pop bypass mode for recording all analog sources, which are often further processed and combined with other pcm data to be output directly to the dac outputs which are configured in pop_bypass mode using the general purpose register (index 20h). d15 d14 d13 d12 d11 d10 d9 d8 00 00000 0 d7 d6 d5 d4 d3 d2 d1 d0 00 00000 0 d15 d14 d13 d12 d11 d10 d9 d8 reserved ac97 all mix reserved d7 d6 d5 d4 d3 d2 d1 d0 rsvd mute fix disable adcslt1 adcslt0 reserved 20/30 sel splyovr en splyovr val stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 52 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.25.2. adc data on ac link bits d5-d4 select slots for adc data on aclink. 6.5.25.3. mutefix disable bit d6 controls the enable and disable of the mutefix functions. 0 = mute fix enabled 1 = mute fix disabled when this bit is zero, and either channel is set to -46.5db attenuation (1fh), then that channel is fully muted. when this bit is one, then operation is per ac?97 specification. this bit is reserved in revisions prior to cc1. 6.5.25.4. mic boost select the mic boost value can be selected with bit d2, which in enabled by register 0eh, bit d6. writing a zero to bit d2 will provide 20db of mic boost. writing a one will provide 30db of mic boost. 6.5.25.5. supply override select the supply override bit, d1, allows override of the supply detect. writing a zero disables the over- ride on supply detect. writing a one, overrides supply detect with bit d0. bit d0 provides the supply override value. a zero forces 3.3 v analog operation and one forces 5 v analog operation. table 36. adc data on ac link value function 00 left slot 3, right slot 4 01 left slot 7, right slot 8 10 left slot 6, right slot 9 11 left slot 10, right slot 11 table 37. mic boost select value function 0 20db 1 30db stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 53 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.25.6. 72h enable (70h) default: 0000h 6.5.25.7. analog current adjust (72h) default: 0000h the analog current adjust register (index 72h) is a locked register and can only be properly written and read from when abbah has been written into register 70h. the ibiasx bits allow the analog cur- rent to be adjusted with minimal reduction in performance. a lower analog current setting is not recommended when a 5v analog supply is used. a lower setting for 3.3v supplies is recommended for notebook computers to reduce power consumption to its lowest level. 6.5.25.8. internal power-on/off anti-pop circuit the stac9750/9751 includes an internal power supply anti-pop circuit that prevents audible clicks and pops from being heard when the codec is powered on and off. this function is accomplished by delaying the charge/discharge of the vref capacitor (pin 27). c vref value of 1 f will cause a turn-on delay of roughly 3 seconds, which will allow the power supplies to stabilize before the codec outputs are enabled. the delay can be extended to 30 seconds if a value of c vref value of 10 f is used. the codec outputs are also kept stable for the same amount of time at power-off to allow the system to be gracefully turned off. the int_apop bit d7 of register 72h allows this delay circuit to be bypassed for rapid production testing. any external component anti-pop circuit is unaf- fected by the internal circuit. d15 d14 d13 d12 d11 d10 d9 d8 en15 en14 en13 en12 en11 en10 en9 en8 d7 d6 d5 d4 d3 d2 d1 d0 en7 en6 en5 en4 en3 en2 en1 en0 d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 int apop reserved ibias1 ibias0 rsvd table 38. analog current adjust ibias1 ibias0 analog current 0 0 normal current 0 1 80% of nominal analog current 1 0 120% of nominal analog current 1 1 140% of nominal analog current stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 54 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.26. gpio access register (74h) default: 0800h the gpio access register requires that the output enable bits (d11, d9 and d8) be used in con- junction with the data source selection (input or output) for the eapd, gpio0 and gpio1 (pins 47, 43 and 44 respectively). for example, to use gpio1 as an output, set d9 = 1 to enable the output, and use d13 to write the output value desired. to use gpio1 as an input, set d9 = 0 to disable the output, and use d13 to read the input value. 6.5.27. high pass filter bypass (index 76h and 78h) the high pass filter bypass register (index 78h) is a locked register and can only be properly written and read from when abbah has been written into register 76h. bit d0 controls the high pass filter bypass. default is zero which provides for normal operation where the high pass filter is active. writ- ing a one, will disable, or bypass the adc high pass filter. 6.5.27.1. 78h enable (76h) default: 0000h d15 d14 d13 d12 d11 d10 d9 d8 eapd reserved gpio1 gpio0 eapd_oen reserved gpio1_oen gpio0_oen d7 d6 d5 d4 d3 d2 d1 d0 reserved table 39. gpio access registers (74h) bit(s) reset value name description 15 0 eapd eapd data output on eapd when bit d11 = 1 eapd data input from pin when bit d11 = 0 14 0 reserved reserved 13 0 gpio1 gpio1 data output on gpio1 when bit d9 = 1 gpio1 data input from pin when bit d9 = 0 12 0 gpio0 gpio0 data output on gpio0 when bit d8 = 1 gpio0 data input from pin when bit d8 = 0 11 1 eapd_oen 0 = eapd data out disabled 1 = eapd data output enabled 10 0 reserved reserved 90gpio1_oen 0 = gpio1 data out disabled 1 = gpio1 data output enabled 80gpio0_oen 0 = gpio0 data out disabled 1 = gpio0 data output enabled 7:0 0 reserved reserved d15 d14 d13 d12 d11 d10 d9 d8 en15 en14 en13 en12 en11 en10 en9 en8 d7 d6 d5 d4 d3 d2 d1 d0 en7 en6 en5 en4 en3 en2 en1 en0 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 55 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 6.5.27.2. adc high pass filter bypass(78h) default: 0000h 6.5.28. vendor id1 and id2 (index 7ch and 7eh) these two registers contain four 8-bit id codes. the first three codes have been assigned by microsoft using their plug and play vendor id methodology. the fourth code is an idt assigned code identifying the stac9750/9751. the id1 register (index 7ch) contains the value 8384h, which is the first (83h) and second (84h) characters of the microsoft id code. the id2 register (index 7eh) contains the value 7650h, which is the third (76h) of the microsoft id code, and 50h which is the stac9750/9751 id code. note: the lower half of the vendor id2 register (index 7eh) currently contains the value xxh identifying the stac9750/9751. this value can be used by the audio driver, or miniport driver in the case of win98 ? , to adjust software functionality to match the feature-set of the stac9750/9751. this portion of the register will likely contain different values if the software profile of the stac9750/9751 changes, as in the case of silicon level device modifications. this will allow the software driver to identify any required operational differences between the existing stac9750/9751 and any future versions. 6.5.28.1. vendor id1 (7ch) default: 8384h 6.5.28.2. vendor id2 76xx (7eh) default: 7650h d15 d14 d13 d12 d11 d10 d9 d8 reserved d7 d6 d5 d4 d3 d2 d1 d0 reserved adc hpf byp d15 d14 d13 d12 d11 d10 d9 d8 10 00001 1 d7 d6 d5 d4 d3 d2 d1 d0 10 00010 0 d15 d14 d13 d12 d11 d10 d9 d8 01 11011 0 d7 d6 d5 d4 d3 d2 d1 d0 01 01000 0 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 56 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 7. low power modes the stac9750/9751 is capable of operating at reduced power when no activity is required. the state of power-down is controlled by the powerdown register (26h). there are 7 commands of sep- arate power down. the power down options are listed in table 40. the first three bits, pr0..pr2, can be used individually or in combination with each other, and control power distribution to the adcs, dacs and mixer. the last analog power control bit, pr3, affects analog bias and reference voltages, and can only be used in combination with pr0, pr1, and pr2. pr3 essentially removes power from all analog sections of the codec, and is generally only asserted when the codec will not be needed for long periods. pr0 and pr1 control the pcm adcs and dacs only. pr2 and pr3 do not need to be ?set? before a pr4, but pr0 and pr1 must be ?set? before pr4. pr5 disables the internal codec clock and requires an external cold reset for recovery. pr6 disables the headphone driver amplifier for additional analog power saving. the figure 19 illustrates one example procedure to do a complete power down of stac9750/9751. from normal operation, sequential writes to the powerdown register are performed to power down stac9750/9751 a piece at a time. after everything has been shut off, a final write (of pr4) can be executed to shut down the ac-link. the part will remain in sleep mode with all its registers holding their static values. to wake up, the ac'97 controller will send an extended pulse on the sync line, issuing a warm reset. this will restart the ac-link (resetting pr4 to zero). the stac9750/9751 can also be woken up with a cold reset. a cold reset will reset all of the registers to their default states. when a section is powered back on, the powerdown control/status register (index 26h) should be read to verify that the section is ready (stable) before attempting any operation that requires it. figure 19. example of stac9750/9751 powerdown/powerup flow table 40. low power modes grp bits function pr0 pcm in adcs & input mux powerdown pr1 pcm out dacs powerdown pr2 analog mixer power down (vref still on) pr3 analog mixer power down (vref off) pr4 digital interface (ac-link) power down (external clock off) pr5 internal clock disable pr6 powerdown headphone_out warm reset cold reset ready =1 normal adcs off pr0 dacs off pr1 analog off pr2 or pr3 digital i/f off pr4 shut off ac-link default pr0=0 & adc=1 pr1=0 & dac=1 pr2=0 & anl=1 pr0=1 pr1=1 pr2=1 pr4=1 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 57 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs figure 20 illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. this configuration can be used when playing a cd (or exter- nal line_in source) through stac9750/9751 to the speakers, while most of the system in low power mode. the procedure for this follows the previous except that the analog mixer is never shut down. figure 20. stac9750/9751 powerdown/powerup flow with analog still active warm reset normal adcs off pr0 dacs off pr1 digital i/f off pr4 shut off ac-link pr0=0 & adc=1 pr1=0 & dac=1 pr0=1 pr1=1 pr4=1 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 58 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 8. multiple codec support the stac9750/9751 provides support for the multi-codec option according to the intel ac'97, rev 2.2 specification. by definition there can be only one primary codec (codec id 00) and up to three secondary codecs (codec ids 01, 10, and 11). the codec id functions as a chip select. secondary devices therefore have completely orthogonal register sets; each is individually accessi- ble and they do not share registers. 8.1. primary/secondary codec selection in a multi-codec environment the codec id is provided by external programming of pins 45 and 46 (cid0 and cid1). the cid pin electrical function is logically inverted from the codec id desig- nation. the corresponding pin state and its associated codec id are listed in the ?codec id selection? table. also see slot assignment discussion, ?multi-channel programming register (index 74)?. 8.1.1. primary codec operation as a primary device the stac9750/9751 is completely compatible with existing ac'97 definitions and extensions. primary codec registers are accessed exactly as defined in the ac'97 component specification and ac'97 extensions. the stac9750/9751 operates as primary by default, and the external id pins (45 and 46), have internal pull-ups so that these pins may be left as no-connects for primary operation. when used as the primary codec, the stac9750/9751 generates the master ac-link bit_clk for both the ac'97 digital controller and any secondary codecs. the stac9750/9751 can support up to four loads of 10 k ? and 50 pf on the bit_clk line. this is to ensure that implementations of up to four codecs will not load down the clock output. 8.1.2. secondary codec operation when the stac9750/9751 is configured as a secondary device the bit_clk pin is configured as an input at power up. using the bit_clk provided by the primary codec insures that everything on the ac-link will be synchronous. as a secondary device it can be defined as codec id 01, 10 or 11 in the two-bit field(s) of the extended audio and/or extended modem id register(s). table 41. codec id selection cid1 state cid0 state codec id codec status dvdd or floating dvdd or floating 00 primary dvdd or floating 0 v 01 secondary 0 v dvdd or floating 10 secondary 0 v 0 v 11 secondary stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 59 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 8.2. secondary codec regi ster access definitions the ac'97 digital controller can independently access primary and secondary codec registers by using a 2-bit codec id field (chip select) which is defined as the lsbs of output slot 0. for sec- ondary codec access, the ac'97 digital controller must invalidate the tag bits for slot 1 and 2 command address and data (slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into the codec id field (slot 0, bits 1 and 0). as a secondary codec, the stac9750/9751 will disregard the command address and command data (slot 0, bits 14 and 13) tag bits when it sees a 2-bit codec id value (slot 0, bits 1 and 0) that matches its configuration. in a sense the secondary codec id field functions as an alternative valid command address (for secondary reads and writes) and command data (for secondary writes) tag indicator. secondary codecs must monitor the frame valid bit, and ignore the frame (regardless of the state of the secondary codec id bits) if it is not valid. ac'97 digital controllers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the secondary codec id bits are set. this method is designed to be backward compatible with existing ac'97 controllers and codecs. there is no change to output slot 1 or 2 definitions. table 42. secondary codec register access slot 0 bit definitions output tag slot (16-bits) bit description 15 frame valid 14 slot 1 valid command address bit (? primary codec only) 13 slot 2 valid command data bit (? primary codec only) 12-3 slot 3-12 valid bits as defined by ac'97 2 reserved (set to 0) ?1-0 2-bit codec id field (00 reserved for primary; 01, 10, 11 indicate secondary) note: ? new definitions for secondary codec register access stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 60 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 9. testability the stac9750/9751 has two test modes. one is for ate in-circuit test and the other is restricted for idt?s internal use. stac9750/9751 enters the ate in-circuit test mode if sdata_out is sampled high at the trailing edge of reset#. once in the ate test mode, the digital ac-link outputs (bit_clk and sdata_in) are driven to a high impedance state. this allows ate in-circuit testing of the ac'97 controller. use of the ate test mode is the recommended means of removing the codec from the ac-link when another codec is to be used as the primary. this case will never occur dur- ing standard operating conditions. once either of the two test modes have been entered, the stac9750/9751 must be issued another reset# with all ac-link signals held low to return to the normal operating mode. stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 61 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 10. pin description figure 21. stac9750/9751 pin description drawing pin 48: to enable spdif, use an 1 k ? -10 k ? external pulldown. to disable spdif, use an 1 k ? -10 k ? external pullup. do not leave pin 48 floating. the cd_gnd signal is an ac signal return for the two cd input channels. it is normally biased at about 2.5v. the name of the pin in the ac97 specification is cd_gnd, and this has confused many designers. it should not have any dc path to gnd. connecting the cd_gnd signal directly to ground will change the internal bias of the entire codec, and cause significant distortion. if there is no analog cd input, then this pin can be no-connect dvdd1 1 xtl_in 2 xtl_out 3 dvss1 4 sdata_out 5 bit_clk 6 dvss2 7 sdata_in 8 dvdd2 9 sync 10 reset# 11 pc_beep 12 24 line_in _r 23 line_in _l 22 mic2 21 mic1 20 cd_r 19 cd_gnd 18 cd_l 17 video_r 16 video_l 15 aux_r 14 aux_l 13 phone 36 line_out_r 35 line_out_l 34 nc 33 nc 32 cap2 31 nc 30 afilt2 29 afilt1 28 vrefout 27 vref 26 avss1 25 avdd1 m ono_out 37 avdd2 38 hp_out_l 39 hp_comm 40 hp_out_r 41 avss2 42 gpio0 43 gpio1 44 cid0 45 cid1 46 eapd 47 spdif 48 48-pin lqfp stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 62 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 10.1. digital i/o these signals connect the stac9750/9751 to its ac'97 controller counterpart, an external crystal, multi-codec selection and external audio amplifier. table 43. digital connection signals pin name pin # type description xtl_in 2 i 24.576 mhz crystal or external clock source xtl_out 3 i/o 24.576 mhz crystal or ground if external clock source connected to xtal_in sdata_out 5 i serial, time division multiplexed, ac'97 input stream bit_clk 6 i/o 12.288 mhz serial data clock sdata__in 8 o serial, time division multiplexed, ac'97 output stream sync 10 i 48 khz fixed rate sample sync reset# 11 i ac'97 master h/w reset nc 31 i/o no connect nc 33 i/o no connect nc 34 i/o no connect gpio0 43 i/o general purpose i/o gpio1 44 i/o general purpose i/o cid0 45 i multi-codec id select - bit 0 cid1 46 i multi-codec id select - bit 1 eapd 47 i/o external amplifier power down spdif 48 o spdif digital output pin 48: - to enable spdif, use an 1 k ? -10 k ? external pulldown. to disable spdif, use an 1 k ? -10 k ? external pullup. do not leave pin 48 floating. stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 63 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 10.2. analog i/o these signals connect the stac9750/9751 to analog sources and sinks, including microphones and speakers. * any unused input pins should be tied together through a capacitor (0.1 f suggested) to ground, except the mic inputs which should have their own capacitor to ground if not used. ? the cd_gnd signal is an ac signal return for the two cd input channels. it is normally biased at about 2.5 v. the name of the pin in the ac?97 specification is cd_gnd, and this has confused many designers. it should not have any dc path to gnd. connecting the cd_gnd signal directly to ground will change the internal bias of the entire codec, and cause significant distortion. if there is no analog cd input, then this pin can be no-connect table 44. analog connection signals pin name pin # type description pc-beep 12 i* pc speaker beep pass-through phone 13 i* from telephony subsystem speakerphone (or dlp - down line phone) aux_l 14 i* aux left channel aux_r 15 i* aux right channel video_l 16 i* video audio left channel video_r 17 i* video audio right channel cd_l 18 i* cd audio left channel cd_gnd 19 i* cd audio analog signal return ? cd_r 20 i* cd audio right channel mic1 21 i* desktop microphone input mic2 22 i* second microphone input line_in_l 23 i* line in left channel line_in_r 24 i* line in right channel line_out_l 35 o line out left channel line_out_r 36 o line out right channel mono_out 37 o to telephony subsystem speakerphone (or dlp - down line phone) hp_out_l 39 o headphone out left channel hp_comm 40 o headphone ground return hp_out_r 41 o headphone out right channel stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 64 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 10.3. filter/references/gpio these signals are connected to resistors, capacitors, specific voltages, or provide general purpose i/o. 10.4. power and ground signals table 45. filtering and voltage references signal name pin number type description vref 27 o analog ground (0.45 * vdd, at 5 v; 0.41 * vdd at 3 v) vrefout 28 o reference voltage out 5 ma drive (intended for mic bias) (~vdd/2) afilt1 29 o anti-aliasing filter cap - adc left channel afilt2 30 o anti-aliasing filter cap - adc right channel cap2 32 o adc reference cap table 46. power and ground signals pin name pin # type description avdd1 25 i analog vdd = 5.0 v or 3.3 v avdd2 38 i analog vdd = 5.0 v or 3.3 v (headphone power source) avss1 26 i analog gnd avss2 42 i analog gnd dvdd1 1 i digital vdd = 3.3 v dvdd2 9 i digital vdd = 3.3 v dvss1 4 i digital gnd dvss2 7 i digital gnd stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 65 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 11. ordering information ordering information note: when ordering these parts the ?yy? will be replaced with the codec revision. add an ?r? to the end of any of these part numbers for delivery on tape and reel. the minimum order quantity for tape and reel is 2,000 units. part number package temp range supply range STAC9750XXTAEYYX 48-pin rohs lqfp 7mm x 7mm x 1.4mm 0 c to +70 c dvdd = 3.3v, avdd = 5.0v stac9751xxtaeyyx 48-pin rohs lqfp 7mm x 7mm x 1.4mm 0 c to +70 c dvdd = 3.3v, avdd = 3.3v stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 66 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 12. package drawings 12.1. 48-pin lqfp figure 22. package drawing - 48-pin lqfp key lqfp dimensions in mm min. nom. max. a1.401.501.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 d8.809.009.20 d1 6.90 7.00 7.10 e8.809.009.20 e1 6.90 7.00 7.10 l0.450.600.75 e0.50 c0.09 - 0.20 b0.170.220.27 48 pin lqfp e e1 d d1 pin 1 b a a2 a 1 c e stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 67 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 13. solder reflow profile 13.1. standard reflow profile data note: these devices can be hand soldered at 360 o c for 3 to 5 seconds. from: ipc / jedec j-std-020c ?moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices? (www.jedec.org/download). figure 23. reflow profile profile feature pb free assembly average ramp-up rate (ts max - tp) 3 o c / second max preheat temperature min (ts min ) temperature max (ts max ) time (ts min - ts max ) 150 o c 200 o c 60 - 180 seconds time maintained above temperature (t l ) time (t l ) 217 o c 60 - 150 seconds peak / classification temperature (tp) see ?package classification reflow temperatures? on page 68. time within 5 o c of actual peak temperature (tp) 20 - 40 seconds ramp-down rate 6 o c / second max time 25 o c to peak temperature 8 minutes max note: all temperatures refer to topside of the package, measured on the package body surface. stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 68 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 13.2. pb free process - package classification reflow temperatures package type msl reflow temperature lqfp 48-pin 3 260 o c* stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 69 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 14. appendix a: split inde pendent power supply operation in pc applications, one power supply input to the stac9750/9751 may be derived from a supply regulator (as shown in figure 24) and the other directly from the pci power supply bus. when power is applied to the pc, the regulated supply input to the ic will be applied some time delay after the pci power supply. without proper on-chip partitioning of the analog and digital circuitry, some manu- facturer's codecs would be subject to on-chip scr type latch-up. idt?s stac9750/9751 specifically allows power-up sequencing delays between the analog (avddx) and digital (vdddx) supply pins. these two power supplies can power-up independently and at dif- ferent rates with no adverse effects to the codec. the ic is designed with independent analog and digital circuitry that prevents on-chip scr type latch-up. however, the stac9750/9751 is not designed to operate for extended periods with only the analog supply active. note: pin 48: to enable spdif, use a 1 k ? -10 k ? external pulldown. to disable spdif, use a 1 k ? -10 k ? external pullup. do not leave pin 48 floating. stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 70 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs figure 24. stac9750/9751 split independent power supply operation typical connection diagram 0.1 f 1 f 0.1 f 0.1 f 10 f 0.1 f *suggested avdd1 avdd2 dvdd1 dvdd2 xtl_in xtl_out 9 2 3 27 pf 27 pf 24.576 mhz 1 38 25 pc_beep 12 phone 13 aux_l 14 aux_r 15 video_l 16 video_r 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 41 32 *optional 0.1 f 1 f* 820 pf 29 30 820 pf avss1 avss2 26 42 4 7 dvss1 dvss2 hp_out_r *terminate ground plane as close to codec as possible analog ground digital ground hp_out_l 39 37 mono_out 36 line_out_r 35 line_out_l 43 44 40 48 34 33 31 0.1 f 1 f* 27 vrefout eapd cid1 cid0 28 47 46 45 11 reset# 10 sync 24 bit_clk sdata_out 5 6 8 27 pf 22 ? emi filter 3.3v 5% 3.3v or 5v 5% optional *optional cap2 afilt1 afilt2 gpio0 gpio1 hp_comm spdif nc nc nc vref sdata_in stac9750 stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 71 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 15. appendix b: programming registers note: all registers not shown, and those labeled ?reserved?, can be written to but are ?don?t care? on read back. note: pc_beep defaults to 0000h, mute off. reg # name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset rsrvd se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 6990h 02h master volume mute rsrvd ml5 ml4 ml3 ml2 ml1 ml0 reserved mr5 mr4 mr3 mr2 mr1 mr0 8000h 04h hp_out mixer volume mute rsrvd hpl5 hpl4 hpl3 hpl2 hpl1 hpl0 reserved hpr5 hpr4 hpr3 hpr2 hpr1 hpr0 8000h 06h master volume mono mute reserved mm5 mm4 mm3 mm2 mm1 mm0 8000h 0ah pc_beep volume mute reserved pv3 pv2 pv1 pv0 rsrvd 0000h 0ch phone volume mute reserved gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute reserved boosted rsrvd gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 1ah record select reserved sl2 sl1 sl0 reserved sr2 sr1 sr0 0000h 1ch record gain mute reserved gl3 gl2 gl1 gl0 reserved gr3 gr2 gr1 gr0 8000h 20h general purpose pop byp rsrvd 3d reserved mix ms lpbk reserved 0000h 22h 3d control reserved dp3 dp2 reserved 0000h 24h audio interrupt i4 i3 reserved i0 reserved 0000h 26h powerdown ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 reserved ref anl dac adc 000fh 28h extended audio id id1 id0 reserved rev1 (0) rev0 (1) amap ldac sdac cdac dsa1 dsa0 rsvd spdif dra vra 0605h 2ah extended audio control/ status reserved spcv rsrvd spsa1 spsa0 rsrvd spdif rsrvd vra enable 0400h 2ch pcm dac rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 32h pcm lr adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 3ah spdif control #v drs spsr1 spsr2 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy #pcm/ audio pro 2a00h 3eh extended modem status reserved pra reserved gpio 0100h 4ch gpio pin config reserved gc1 (gpio1) gc0 (gpio0) 0300h 4eh gpio pin polarity/type reserved gp1 (gpio1) gp0 (gpio0) ffffh 50h gpio pin sticky reserved gs1 (gpio1) gs0 (gpio0) 0000h 52h gpio pin mask reserved gw1 (gpio1) gw0 (gpio0) 0000h 54h gpio pin status reserved gi1 (gpio1) gi0 (gpio0) 0000h 60h z_data volume mute reserved gl4 gl3 gl2 gl1 gl0 reserved gr4 gr3 gr2 gr1 gr0 8808h 6ah digital audio control reserved do1 do0 0000h 6ch revision code 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00xxh 6eh analog special reserved ac97 all mix reserved mute fix disble adcslot1 adcslot0 rsvd mic gain value sply ovr en sply ovr val 1000h 70h 72h enable en15 en14 en13 en12 en11 en10 en9 en8 en7 en6 en5 en4 en3 en2 en1 en0 0000h 72h analog current adjust reserved int apop reserved ibias<1:0> rsvd 0000h 74h * gpio access eapd rsvd gpio1 gpio0 eapd_oen reserved gpio1_oen gpio0_oen reserved 0000h 76h 78h enable en15 en14 en13 en12 en11 en10 en9 en8 en7 en6 en5 en4 en3 en2 en1 en0 0000h 78h high pass filter bypass rseserved adc hpf byp 0000h 7ch vendor id1 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 8384h 7eh vendor id2 9750 0 1 1 1 0 1 1 0 0 1 0 1 0 0 0 0 7650h stac9750/9751 value-line two-channel ac?97 codecs pc audio idt? 72 stac9750/9751 v 5.8 103106 value-line two-channel ac?97 codecs 16. revision history revision date description of change 5.2 october 2003 corrected error on page 26: slot 1 status address port, bit d2 is a slot request not reserved as stated in rev 5.1 added cd_gnd elaboration note on connection diagram, pin list and pin out diagrams: the cd_gnd signal is an ac signal return for the two cd input channels. it is normally biased at about 2.5v. the name of the pin in the ac97 specification is cd_gnd, and this has confused many designers. it should not have any dc path to gnd. connecting the cd_gnd signal directly to ground will change the internal bias of the entire codec, and cause significant distortion. if there is no analog cd input, then this pin can be no-connect. 5.3 june 2004 corrected note 4 in performance characteristics, was missing the text ?ratio of full scale signal to thd+n output with -3db signal, measured ?a weight ed? over a?. complete note now reads ?ratio of full scale signal to thd+n output with -3db signal, measured ?a weighted? over a 20 hz to a 20 khz bandwidth. 48 khz sample frequency?. 5.4 january 2005 added updated 48-pin package drawing. added reflow profile information. 5.5 february 2005 revised reflow profile information 5.6 march 2005 revised tqfp to say lqfp. 5.7 december 2005 updated with new logo template added part order information for rohs package, with eol information to pb-bearing removed references to older revisions (ca3) and their relationship to cc1, as ca3 is eol and cc1 is the only production revision. 5.8 30 october 2006 initial release in idt format. ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support ha.cm@idt.com innovate with idt audio for high fidelity. contact: www.idt.com stac9750/9751 value-line two-channel ac?97 codecs pc audio |
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